User guide

• Intersymbol interference
• Level noise
This refers particularly to the performance of phase-locked loops (PLLs) or clock
data recovery circuits (CDR).
Jitter tolerance can be measured by applying a distorted data signal to the DUT
and measuring the resulting bit error ratio. To make jitter tolerance tests
reproducible, the signal distortion must also be reproducible. This requires some
definitions.
Jitter
Receivers react differently on
• different types of jitter
• the jitter composition
• the jitter frequency spectrum
• the combination of jitter frequencies and data rate
Various test standards specify the jitter composition to be used for jitter tolerance
tests.
The Serial BERT provides the following means for generating artificial
(reproducible) jitter:
• Two types of voltage-controlled signal delay lines
• A phase shifter for modulating the generated clock
For more information see
• “Understanding the Types of Jitter” on page 397
• “How the N4903 Generates Jitter” on page 401
Intersymbol Interference
Conductors on PC boards have a limited bandwidth. This causes intersymbol
interference which changes the shape of the received eye opening. The eye
becomes unsymmetrical.
The Serial BERT provides the Interference Channel option J20 to simulate ISI.
For more information see
• “Intersymbol Interference” on page 399
Level Noise
Level noise affects the voltage amplitude of the eye opening.
8 Jitter Tolerance Tests
396 Agilent J-BERT N4903B High-Performance Serial BERT