User guide

Table 21
Parameter Values
Begin Margin CDR Settling Time + Synchronization
Time
End Margin Valid after Gate
Bit Count Time Burst Length - Begin Margin - End Margin
Gate Active Begin Margin + Bit Count Time
Optimizing the Timing
There are three things to watch when optimizing the timing for burst sync mode:
• BER
The bit error rate increases when the gate closes too late. The duration of the
signal should typically be reduced.
• Burst sync ratio
The burst sync ratio is an indication of how much of the burst signal is in
synchronization (and can therefore be used for counting bit errors). The higher
the value, the better.
• Bad burst count
The bad burst count counts the number of bursts that are invalid (for example,
because synchronization failed or the BER of a synchronized burst exeeds the
sync threshold).
The following describes how changing the Gate In start and end points can affect
the evaluation of bursts.
Starting too soon: If the Gate In signal is applied too soon, the error detector will
either not be able to recover the clock or synchronize the pattern, and will thus
mark the burst as a bad burst (thus increasing the bad burst count). You can
typically reduce the bad burst count by starting the gating period later.
Burst
Attempted Settling Time ends here
Start too soon
CDR Settling Time
Synchronization Time
Settling/Synchronization fail hereGate Input
Data Input
Setting up the Error Detector 5
Agilent J-BERT N4903B High-Performance Serial BERT 215
Gate In Start