User guide

The Bit Count Time is the part of the burst from which the bits can actually be
counted. The remainder of the burst is covered by the Begin Margin and End
Margin.
The CDR Settling Time is the time that the error detector requires in CDR mode to
get the clock from the data stream.
The Synchronization Time is the time the error detector requires to synchronize
to the pattern. This time depends on the pattern type (PRBS or memory-based).
The Valid after Gate indicates the minimum length of data that has to arrive at
Data In after the Gate In signal is deactivated.
There is no requirement how long a signal should be available at Data In before
gating starts (the data should simply be stable). A pause is however required after
the gating to allow the error detector to evaluate the results. This time is known
as Gate Passive.
The following is a summary of the values of these parameters for the Serial
BERT:
Table 20
Parameter Values
Bit Count Time Min.: 1536 bits
Max: 4 Gbits
The optimal length is dependent on the
BER threshold.
CDR Settling Time CDR mode: 2 microseconds
Non-CDR mode: 0
Synchronization Time Hardware PRBS: 1536 bits
Memory-based patterns: Min. 15 kbits
(depends on when and how often the
unique word occurs)
Valid after Gate CDR mode: 1.5 microseconds
Non-CDR mode: 1536 bits
Gate Passive CDR mode: 2560 bits or 1.5 microseconds
(whichever is larger)
Non-CDR mode: 2560 bits
The following values can be derived from these parameters:
5 Setting up the Error Detector
214 Agilent J-BERT N4903B High-Performance Serial BERT
Interval between Bursts