User guide

How Burst Sync Mode Works
The following figure presents the basic order of events that make up a burst mode
measurement. It also illustrates how the instrument operates while in burst mode.
Gate In?
no
CDR?
yes
yes
Sync?
CDR Settling Time
Synchronization Time
no
BER
OK?
success
failed
Total Burst + 1
Bad Burst +1
Incr. Bit Counters
yes
no
Register Incoming Bits
Gate In?
no
yes
1
2
3
4
5
6
7
N O T E
Burst mode requires a complete measurement setup, including an external input
for the Gate In port. This input is used for the sync alignment.
1
Burst sync is started when the Gate In signal goes low, indicating that a burst
is arriving at the Data In port.
2
If the error detector is in CDR mode, it first tries to generate a clock from the
data. A short time interval is required to stabilize the clock (the CDR settling
time).
Note that if the error detector is in CDR mode, it is necessary to set a CDR
threshold. This is the BER threshold that the error detector uses to verify that
the input pattern is synchronized. See “How does Clock Data Recovery Work?”
on page 174 for more information.
If an external clock is used, there is no delay. The clock signal must however
be continuous.
5 Setting up the Error Detector
212 Agilent J-BERT N4903B High-Performance Serial BERT