User guide

The usage of the enhanced error detector trigger is based on the PCIe3 SKPOS
(Skip Ordered Set). The 130 bit SKPOS is used as detect word and is not
configurable. The SKPOS removal unit triggers upon a detected word of 66, 98,
130, 162 and 194 bit SKPOS which is used with the pattern generator AUX input
to advance a pattern sequence and thus implements a simple handshake. The
enhanced error detector trigger capability is only available when the 128B/
130B coding support is activated. Only the trigger pulse timing is compatible
with the pattern generator Aux input for sequence advance. It takes 2048 bit
time period to process the trigger and the signal is active only for half of this
period. Hence next trigger will be processed only after this period.
N O T E
The SKPOS Detected option will be available only if you have selected the error
ratio based on Bit Comparison without PCI3 SKPOS.
Note, that the length of the trigger signal is at least 40 bits and divisible by 4.
Aux Out
You have two options to set up the signal at the Aux Out port:
•
Clock
This option supplies the clock signal to the Aux Out port.
•
Data
This option supplies the data signal via a comparator to the Aux Out port.
The comparator is controlled by the 0/1 threshold. This lets you use an
oscilloscope to determine if the 0/1 threshold is correctly set. If the 0/1
threshold is set below or above the data eye, the output at Aux Out will be
constant high or low, respectively.
Pattern Synchronization
Pattern Synchronization - Concepts
The Serial BERT calculates bit error rates by comparing the received data with the
expected data patterns. To do this, it needs to know where the start of the pattern
is located in the data stream.
Setting up the Error Detector 5
Agilent J-BERT N4903B High-Performance Serial BERT 205