User guide

Sampling Point Setup
Sampling Point Setup - Concepts
This section provides basic information on the sampling point setup and eye
diagrams.
How Does the Sampling Point Setup Work?
The sampling point of a data signal is defined by two values: a point in time and a
voltage level. Each bit of the data signal is sampled at this point in time and in
reference to this voltage level. The point in time (in reference to the clock signal)
is referred to as the data input delay, and the voltage level is referred to as the 0/1
decision threshold.
The location of the sampling point is the decision factor as to whether the incoming
bits are identified as logic 0's or 1's. To measure the accurate bit error ratio at the
input port, false readings of logic 0's or 1's must be avoided. Therefore, the
sampling point must be set to the optimum location within the data eye.
The functions within the Sampling Point Setup window allow you to:
• Prepare the error detector for the incoming data signal regarding the connector
termination.
• Graphically display the eye diagram in terms of voltage, input delay and a BER
threshold.
• Adjust the location of the sampling point.
What is an Eye Diagram?
An eye diagram provides a way to view all possible transitions between adjacent
bits of a data stream by overlaying them on the display of a high-speed oscilloscope.
It is typically produced by triggering the oscilloscope with a synchronous clock
signal.
When the oscilloscope is triggered by a clock signal, data patterns will not be
examined. Instead, if persistence is set high enough, the shape of an "eye" will be
Setting up the Error Detector 5
Agilent J-BERT N4903B High-Performance Serial BERT 193