User guide

• press the Measure button to measure the voltage level of the incoming signal
while a burst signal is applied.
Once the level is defined, it remains fixed for the following measurements.
Note that the entered voltage level has to be within the input range of the error
detector. If the value lies outside this range, the change is rejected and an error
message is displayed.
CDR Spread Spectrum Clocking
This control is used to adapt the CDR to an input bit stream with SSC. Enable widens
the loss of lock detection window, and sets the peaking to optimum SSC
performance. Enter the Expected Deviation and the type of deviation (Upspread,
Downspread or Centerspread) to set the locking window to an optimum.
SSC is mostly used “down-spread” which means, the clock signal is modulated to
a lower frequency and back. Thus the average frequency is lowered by half of the
maximum deviation. The CDR is adapted to that value. Enter the maximum deviation
as most standards specify.
N O T E
Although the CDR will lock even without the presence of SSC, it is strongly
recommended to uncheck this box when SSC is not present; otherwise the CDR will
unnecessarily loose performance in lock detection and lock time.
Error Ratio
Error Ratio - Concepts
The Serial BERT provides the enhanced capability to perform a receiver (RX) jitter
tolerance test where it analyses 10 bits symbols as coded data to measure Symbols
Error Ratio (SER), Frame Error Ratio (FER), Filler Symbol Ratio (FSR), Illegal Symbol
Ratio (ISR), Disparity Error Ratio (DER) along with the calculated BER (cBER).
You need to set the error ratio mode from Comparison the J-BERT's Error Detector
- Error Ratio window. For more information, see “Setting up Error Ratio” on page
185.
5 Setting up the Error Detector
182 Agilent J-BERT N4903B High-Performance Serial BERT