Specifications

January – March 2003 ExtroNews 14.1 7
TECHNICALLY SPEAKING...
continued on next page
have certain features that favor efficient SDI
transmission. The most notable is
“reclocking,” which occurs at the receiver
front end. Reclocking is a multi-step
restoration process in which the digital signal
is terminated in 75 ohms, the signal level
equalized, the embedded data clock signal
extracted and used to clock a data latch;
after which the data level and timing is
restored close to the original signal quality.
Reclocking circuits involve stable phase-
locked loop (PLL) circuitry whose job it is to
lock onto the recovered clock signal and
“clean up” the data by squaring up the
edges while removing most noise and timing
jitter (See Figure 2). Most SDI routers have
reclocking circuits at the front end, back end,
or both, depending on matrix architecture
and size. SDI distribution amplifiers typically
utilize reclocking at the front end. This
feature is intended to clean up signal timing
jitter so as to extend transmission distance,
just as one might install line amplifiers in an
RF distribution system to extend transmission
distance. The two key forces affecting SDI
transmission negatively are amplitude loss
and timing jitter. If you design long distance
SDI distribution systems and want to
maximize distance and minimize risk, then
reclocked devices are a must. This is
particularly important for multiple
connection schemes involving routers.
Do you always need reclocking in a
distribution device? No, with some
qualification. Some SDI distribution situations
could be run, without reclocking, through
DAs and routers. Non-reclocked paths can
work for the following reasons
1
:
• Good intrinsic signal fidelity in the signal
routing system.
• Permanent path exists from an SDI
device generating a pristine serial output, to
a processing device having a receiver with
good input jitter tolerance versus frequency.
• A well-designed serial digital receiver
with a much wider input jitter tolerance (IJT)
than an intermediate reclocker.
Admittedly, reclocking does complicate
product design and cost. There are times
when this feature can be a disadvantage. A
router/reclocker with a wide PLL bandwidth
in the output stage could inflict jitter on an
otherwise good signal. Wide bandwidth PLLs
are needed mostly at the input of the router.
The PLL range is expected to allow the
system to capture at all SMPTE serial bit
rates.
1
One expects the matrix router
manufacturer to pay careful attention to
this issue.
In contrast, to distribute SDI through an
analog router without reclocking, the
designer must be well aware of system
performance. Steps must be taken to ensure
operation within the serial digital receiver’s
design margins for effective design
PARALLEL
4:2:2 DIGITAL
COMPONENT
VIDEO
PARALLEL
4:2:2 DIGITAL
COMPONENT
VIDEO
27 MHz
CLOCK
27 MHz
CLOCK
10 10
SHIFT
REGISTER
SCRAMBLER
CABLE
DRIVER
CABLE
EQUALIZER
DESCRAMBLER
75-OHM
COAX
270 MHz
CLOCK
SHIFT
REGISTER
SAV, EAV
DETECT
270 MHz
PLL
DIVIDE
BY 10
10x
PLL
Original Data
Data with Noise & Jitter
Clock with Jitter due to Clock Recovery
Recovered Data with Edge Jitter
Figure 2. Data recovery with extracted clock.
Figure 1. 4:2:2 Serial Digital Interface Topology.
implementation and avoidance of service
calls. A receiver designed to work with
SMPTE 259M signals, for example, will
expect to “see” a standard signal attenuated
primarily by the coaxial cable frequency
response losses. Any deviation from a
nominal -6db/octave roll-off over a
bandwidth of one megahertz to the clock
frequency will cause improper operation of
the automatic equalizer in the serial receiver.
2
Analog signal router compliance to this issue
can be difficult to guarantee, even though its
characteristics for analog signals are very
adequate. Considering the complexity of
most analog routers, this risk may not be
worthwhile.
Know the Warning Signs
Let’s say you want to implement an analog
router for SDI. What obstacles are likely to lie
in the road? In my hypothetical analogy, the
posted speed limit would be the usable
bandwidth (-3db point) of the analog
system. It happens, by virtue of its data
coding scheme, a 270 Mbps SDI transmission
corresponds to a 270 MHz bandwidth
requirement. Any analog device having less
than 270 MHz bandwidth (-3db) through
any routing path will significantly affect data
integrity over any long distance by
immediately slowing the data edge rise and
fall times for that path. Further, analog
bandpass response may not always be flat,