User guide

Using NVIDIA Software
EVGA Corporation
January 11, 2008 | DU-03751-001_v01 83
lower cycle time results in better performance but is can instability.
Adjustable from 0 to 6 cycles.
 W to W Timing
The Write-to-Write (tWRWR) timing is the number of clock cycles
between the last write and the subsequent Write command to the same
physical bank. Adjustable from 2 to 15 cycles.
 CAS Latency
The CAS Latency (tCL) is the time (in number of clock cycles) that
elapses after the memory controller sends a request to read a memory
location and before the data is sent to the module's output pins. The
value shown cannot be changed.
 Clock Drive Strength
This value is filled in by the system and can not be changed by the user.
 Command Per Clock
The Command Per Clock (tCPC) sets the Command Rate for the
memory controller. The value shown cannot be changed
 Async Latency
This value is filled in by the system and can not be changed by the user.