User manual

Detailed hardware description

Issue E 33

Flash memory

The ZEUS supports 32MB or 64MB of Spansion (AMD) MirrorBit Flash memory for the

boot loader, OS and application images. The Flash memory is arranged as 128Mbit x 16-

bit (32MB device) or as 256Mbit x 16-bit (64MB device).

The Flash memory array is divided into equally sized symmetrical blocks that are

64-Kword in size (128KB) sectors. A 256Mbit device contains 256 blocks, and a 512Mbit

device contains 512 blocks.

Whenever the Flash memory is accessed the ‘Flash’ access LED is illuminated.

SDRAM

There are two standard memory configurations supported by the ZEUS: 64MB or 128MB

of SDRAM located in banks 0 and 1. The SDRAM is configured as 16MB x 32-bit

(64MB), or 32MB x 32-bit (128MB). 64MB configuration is using 2 devices, and 128MB

configuration is using 4 devices, each with 4 internal banks of 4MB x 16-bit. Optional

256MB configuration is using 4 devices, each with 4 internal banks of 8MB x 16-bit.

These are surface mount devices soldered to the board. The size of memory fitted to the

board is detected by software to configure the SDRAM controller accordingly.

The SDRAM memory controller is set to run at frequency of 104MHz.

Static RAM

The PXA270 processor provides 256KB of internal memory-mapped SRAM. The SRAM

is divided into four banks, each consisting of 64KB.

The ZEUS also has an external 256KB SRAM device fitted, arranged as 256Kbit x 8-bits.

Access to the device is on 16-bit boundaries, whereby the least significant byte is the

SRAM data and the 8-bits of the most significant byte are ‘don’t care’ bits. The reason for

this is that the PXA270 is not designed to interface to 8-bit peripherals. This arrangement

is summarized in the following data bus table:

Most significant byte Least significant byte

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Don’t Care SRAM Data

The external SRAM is non-volatile while the on-board coin cell battery is fitted.

Configuration EEPROM

The configuration EEPROM is interfaced directly to PXA270’s I

C controller. It is a

Microchip 24AA01 1Kbit EEPROM organized as one block of 128 x 8-bit memory.

The configuration EEPROM is addressable at I²C serial bus address 0x50 and is

accessed in fast-mode operation at 400KB/s.