User manual

ZEUS user manual
Issue E
32
Watchdog timer
The ZEUS uses an external watchdog timer (MAX6369) which can be used to protect
against erroneous software. This is a programmable watchdog timer that can be adjusted
for timeout periods of 1ms, 10ms, 30ms, 100ms, 1s, 10s and 60s. The board is reset
when timeout occurs. The MAX6369 watchdog timer can be programmed using the WD
setup register provided within the CPLD. The register is memory mapped (accessible
through CS5#). The WDT is disabled upon reset, and remains so until enabled by the
software.
The following table shows the WD setup register bit definitions:
Watchdog Register [REG3]
Bits Description
7:4 Not used.
3 WDI: Watchdog Input. If WDI remains either high or low for the
duration of the watchdog timeout period (t
WD
), WDT triggers a reset
pulse. The internal watchdog timer clears whenever a reset pulse is
asserted or whenever WDI sees a rising or falling edge.
2:0 WDSET[2:0] – watchdog enable / timeout period setup bits.
Hex Offset Address: 0x13800000
Reset Hex Value: 0x03
Access: Read/write
For further details, see the Intel PXA27x Processor Family Developer’s Manual on the
Development Kit CD.
Memory
The ZEUS has four types of memory fitted:
• 32 or 64MB resident Flash disk containing:
- Boot loader to boot operating system.
- Operating system.
- Application images.
• 64, 128 or 256MB of SDRAM for system memory.
• Static RAM, as follows:
- 256KB of SRAM internal to PXA270.
- 256KB of SRAM external to PXA270 (battery backed).
• 128 bytes of configuration EEPROM on the I²C bus.