User manual

Detailed hardware description
Issue E 19
UART and CPLD address map
PXA270 chip select Physical address Bus width Description
0x10000000 – 0x107FFFFE 16-bit UART 1
0x10800000 – 0x10FFFFFE 16-bit UART 2
0x11000000 – 0x117FFFFE 16-bit UART 3
0x11800000 – 0x11FFFFFE 16-bit UART 4
0x12000000 16-bit REG0 (CPLD Ver/Issue)
0x12800000 16-bit REG1 (PC104 IRQ
status)
0x13000000 16-bit REG2 (CF Reset)
CS4#
0x13800000 16-bit REG3 (WD Register)