Datasheet

VIPER Embedded Linux Development Kit Quickstart Arcom Embedded Linux (AEL)

If you intend to use the PXA255’s internal RTC as a wake up source, you must unload

the driver for the external RTC (which cannot perform the wake up function) and load

the driver for the internal RTC, as follows:

1 Remove the external DS1307 RTC driver:

# rmmod ds1307

2 Install the SA1100/PXA255 RTC driver:

# modprobe sa1100-rtc

3 Resynchronize the SA1100/PXA255 RTC to the correct time from the system

clock:

# hwclock –systohc

The source for the arcom-utils package (which is on the Development Kit CD, in the

/packages/arcom-utils folder) contains the script viper-sleep.sh, which is an example of

how to put a VIPER board to sleep and wake it up again.

LCD controller

The LCD controller driver module (pxafb) is configured by default for the 320x240 TFT

display (part number NL3224BC35), which is an optional part of the VIPER ICE box.

The CYCLOPS image is configured to support the CYCLOPS flat panel (see page 29

The driver module can be loaded using the normal modprobe command:

# modprobe pxafb

In order to use other LCD modules, extra parameters must be passed to the modprobe

command, either on the command line or using one of the methods described in the

AEL Technical Manual. The options are given as a comma separated list of parameters.

Where a parameter requires a value, it is separated from the parameter name using a

colon. The available parameters are listed in the following table. The registers referred

to are described in section 7.6.4 of the PXA255 Processor Developer’s Manual, which

is in the /references/ folder on the Development Kit CD.

Parameter Description Default

mode The required video mode written as:

XRESxYRES-BPP

Where XRES is the X axis resolution, YRES is

the Y axis resolution and BPP is the desired bit

depth.

The hardware supports bit depths of 1, 2, 4, 8 and

16-bits. The LCD driver is known to work well in 8-

or 16-bit mode.

This parameter corresponds to the LCCR1[PPL],

LCCR2[LPP] and LCCR3[BPP] registers.

mode:320x240-16

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