US SER MAN NUAL CP PU-71--15 (D DPD5) Core i7 7 VMEbus SBC S Module e First edition – June J 2013 – DP PD5MAN101 DIGITAL TEC CHNOLOGIES S FOR A BETT TER WORLD www.eurotech.
Preface Thank you for choosing the CPU-71-15. Please read this manual before using the CPU-71-15 so that you may obtain the greatest benefit from using the device. This manual presents the specifications, functions, and method of use of the CPU-71-15. Eurotech has made every effort to carefully inspect each product and has taken great care to package and to ship the product.
Table of Contents Table of Contents Document Revision History ......................................................................................................................... 2 Table of Contents ......................................................................................................................................... 3 1. Important User Information ...................................................................................................................... 5 1.
CPU-71-15 - User Manual 5.1.4. Mechanical Drawing ................................................................................................................... 23 5.2. Power Sequence ................................................................................................................................ 24 6. Connectors, Jumpers, and LEDs ........................................................................................................... 25 6.1. CPU-71-15 Placement Plans ...............
Important User Information 1. Important User Information In order to lower the risk of personal injury, electric shock, fire, or equipment damage, users must observe the following precautions as well as good technical judgment, whenever this product is installed or used. All reasonable efforts have been made to ensure the accuracy of this document; however, Eurotech assumes no liability resulting from any error/omission in this document or from the use of the information contained herein.
CPU-71-15 - User Manual Protect the product from water and chemicals Contact between the product and water or chemicals can result in product failure, electrocution, or fire. Protect the product from foreign material Make sure that foreign material does not get into the product during use, storage, or transport because this can result in product failure. Use precautions in handling to ensure that you are not injured The sharp projections on this product may cause injury.
Important User Information Use antistatic precautions This product comprises electronic parts that are highly susceptible to static electricity. Static electricity can cause the product to malfunction. Take care not to touch any of the terminals, connectors, ICs, or other parts with the hands. Do not use a malfunctioning product Stop using the product if you believe it is malfunctioning.
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Summary 2. Summary CPU-71-15 is a VMEbus Single Board Computer (SBC) Module based on Intel® CoreTM i7 mobile processor. It is compatible with VME64 (ANSI/VITA 1-1994) and VME64x (VITA 1.1-1997) standards which are backwards compatible the original VMEbus Specification (ANSI/IEEE STD1014-1987). Based on Hyper-Threading technology, the Intel® CoreTM i7 2610UE mobile processor enables simultaneous performance of 4 threads on dual-core, and is suited for applications requiring high performance.
CPU-71-15 - User Manual 2.2. Block Diagram CPU-71-15 Block Diagram is shown in Fig.1. Fig.
Hardware Specifications 3. Hardware Specifications 3.1. Processor 3.1.1. Processor Options Intel’s ®CoreTM i7-2610UE Mobile Dual Core CPU at 1.5GHz (TDP:17W) is the off-the-shelf processor, preferable for embedded applications with broader temperature requirements. Intel® Core i7-2655LE Mobile Dual Core CPU at 2.2GHz (TDP:25W) is optional. 3.1.2.
CPU-71-15 - User Manual 3.1.4. Memory Address Map Memory space Address Map is shown in Table 2. Table 2.
Hardware Specifications 3.1.5.2. Status Register (offset：0001h) This register shows the logic of SPD Write Protect signal and input signal from carrier board. Table 5. bit 7..
CPU-71-15 - User Manual 3.2.3. External Memory Interface CPU-71-15 has the following 2 external memory interfaces for mass storage devices and boot options: Serial ATA. CPU-71-15 has two 6 Gb/s SATA ports (SATA0 and SATA1) accessible at the front panel, which can boot from mass storage devices through cable connections. SATA2 is a 3 Gb/s port and it is routed to the optional P0 connector to the backplane.
Hardware Specifications 3.3.2. PCI Express CPU-71-15 is compliant with PCI Express Rev2.0 standard. The CPU has 16 lanes of PCI Express that were discussed in the previous section. The QM67 PCH offers 8 lanes of PCI Express. Table 9 shows how the 8 PCI Express lanes from the PCH are used and what devices they interface to. Table 9.
CPU-71-15 - User Manual 3.3.7. PCI CPU-71-15 has a 32bit/33MHz PCI bus compliant with the PCI Local Bus Specification Revision 2.3 standard. The PCI bus interface is provided by a PLX PEX8112 bridge that adapts from one (x1) PCI Express lane off the QM67 and then is used to interface to the Idt Universe IID PCI bus to VMEbus controller. Additionally it interfaces to the two optional PMC sites. The signal voltage on the PCI bus is 3.3VDC only. PCI devices are shown in Table 12. Table 12.
Hardware Specifications 3.4. I/O CPU-71-15 has the following interfaces to external devices. 3.4.1. GPIO CPU-71-15 has a GPI control register and a GPO control register. The features of GPIO are shown below. 3.4.1.1. GPI CPU-71-15 is equipped with 4 general inputs. They can be read out from the Intel QM67 PCH register. GPI is set as input pin in BIOS. The register where GPI is allocated is shown in Table 13. If the GPI line’s jumper is closed, that GPI line will be connected to its corresponding GPO line.
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Mechanical Specifications 4. Mechanical Specifications CPU-71-15 is compliant with the VMEbus & VME64 Specification. Mechanical specifications are shown in Table 16. Table 15. Characteristic Mechanical Specifications Contents PC Board Form Factor 233.35mm high x 153.67mm wide x 2.31mm thick Backplane Connectors 96 pin DIN 603-2-IEC-CO96Mx-xxx connectors in compliance with the VME64 Draft Specification Weight 680g (Including heat sink and front panel) 4.1.
CPU-71-15 - User Manual 4.2. Fro ont Pan nel The D DPD5’s front panel usess a non-stan ndard length h and a spe ecial captive screw (deta ail G, part # 11408 84RS.375CS SS12). The iridite i finish is Mil-C-5541 1. Fig.3.
Mechanical Specifications 4.3. Heat Sink The CPU-71-15 comes with a heat sink. The heat sink mainly comes in contact with the CPU, the PCH chipset, and the 82571EB dual Ethernet Controller that routes to the backplane. These are the onboard chips with exposed dies. The fins aid in airflow cooled VMEbus chasses as fans must force air from top to bottom or vice versa. The fins will channel the air and add to the surface area that is exposed to forced air. The measurements in the drawing are in mm. Table 16.
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Cautiions for Des signing a Ca arrier Board d 5. PM MC Sup pport and a Po ower Cyclin C ng 5.1. Op ptional PMC P Mo odule Support 5.1.1. Gen neral Versions of th V he CPU-71-15 that suppo ort one or two o PMC sites must be spe ecial ordered d because they confflict mechaniically with the e front panell connectors.. The first sitte, which alsso supports a x8 XMC C interface, will w conflict with w the dual stacked SAT TA connector, 4 of the 5 front f panel USB portts, and the frront panel Etthernet port.
CPU-71-15 - User Manual 5.2. Power Sequence 12V and 5VDC on the VMEbus have no power sequence but 12 VDC is required to switch on the onboard 5 VDC which is the source for all other voltages. For internal use: Turn the board power off when connecting the SF100 programming tool to the CN1 connector for BIOS reprogramming. Do not send the following signals when the CB_RESET# signal is being asserted.
Connectors and Jumpers 6. Connectors, Jumpers, and LEDs 6.1. CPU-71-15 Placement Plans A photograph of the CPU-71-15, component side, is shown in Fig.4 with connectors and major components labelled. The solder side is shown in Fig. 5. Fig. 6 labels user option jumpers and LEDs. PB1 J26 J27 LVDS VGA J28 J1 USB5,4 J2 USB3,2,1 USB PS/2 CPU SATA Battery DRAM SI/O J29 CFast CPU PCH Universe P0 P2 P1 Fig.4 Component side DRAM J6 and J7 CN3 PEX8112 CPLD CN1 Fig.
CPU-71-15 - User Manual 6.2. On-board Jumpers and LEDs JP22 JP1 JP21 JP3 D25 D33 D32 LED1 D36 D34 D24 JP18 JP17 JP19 LED2 JP2 D35 JP6 JP4 JP5 Fig.6 Locations of User Option Jumpers & LEDs 6.2.1. User and Factory Option Jumpers (JPx) The CPU-71-15 has several user (and factory only) jumpers that are shown in figure 6, above. Jumper 26 # of Pins Description JP1 2 Clears CMOS and BIOS settings go to default when shunted for 4 seconds while power is off.
Connectors and Jumpers 6.2.2. On-board LEDs The CPU-71-15 has LEDs that provide info on system status and are shown in figure 6, above. LED Color LED1 Green When LED1 is lit, the on-board power supplies are on and the board should be running. Description LED2 Red When LED2 is lit, the on-board power supplies are in standby mode and the board will not run. D24 Red? D24 is turned on by pin PC8 (LED1) from the CFast drive at connector J25.
CPU-71-15 - User Manual 6.3.5. J2 Dual Front Panel SATA Port Connector Connector J2 provides two SATA ports accessible at the front panel. Both of the two SATA ports in the stacked J2 connector have this same pinout (the TxD pair is driven to J2; the RxD pair is driven from J2): Pin Signal 1 GND 2 TxD+ 3 TxD- 4 GND 5 RxD- 6 RxD+ 7 GND 6.3.6. J26 Front Panel VGA Connector J26 is a high-density DB15 VGA connector accessible from the front panel.
Connectors and Jumpers 6.3.7. J27 Front Panel LVDS Connector J27 is a Single-in-line Molex connector accessible from the front panel that provides a 3 bit differential LVDS flat panel interface. Here is the pinout for J27: Pin Signal 1 GND 2 LVDS_A_CLK+ 3 LVDS_A_CLK- 4 GND 5 LVDS_A2+ 6 LVDS_A2- 7 GND 8 LVDS_A1+ 9 LVDS_A1- 10 GND 11 LVDS_A0+ 12 LVDS_A0- 6.3.8.
CPU-71-15 - User Manual 6.3.10. P1 & P2 & P0 (VMEbus backplane connectors) P1, P2 are the VMEbus connectors populated on standard off-the-shelf CPU-71-15 cards. They are Harting 160-pin 5-row DIN connectors. Table 17 has the pinout for the P1 connector. P1 is VMEbus spec compliant in its pinout while P2 has custom I/O routing of COM ports, SATA, LAN and LPT1. P1 uses a 5-row connector but the two outside rows (D & Z) are all no connects. The P2 pinout is in Table 18.
Connectors and Jumpers Table 18.
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System Specifications 7. System Specifications 7.1. Power Supply Power to the CPU-71-15 is supplied through P1 & P2 (VMEbus backplane connectors), pinout on pages 30 & 31. Power supply specifications are shown in Table 20. Table 20. Item Power supply Current consumption Power supply specifications Unit Symbol Min Typ. Max VCC_12V 11.4 12 12.6 V VCC_5V 4.75 5 5.25 V VCC_RTC 2.0 3 3.3 V IVCC_12VDC - - - A IVCC_5VDC - 4.1 6.2 A IVCC_RTC - 1.4 - μA Max Unit 3.38 V 0.
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BIOS Setup 8. BIOS Setup The CPU-71-15 is equipped with the Phoenix Technologies Ltd. SecureCore Tiano BIOS, customized for this particular board. This chapter describes the BIOS setup procedure. To enter the BIOS setup menus, press the F2 key while immediately after powering up.
CPU-71-15 - User Manual 8.1.4. Boot Features Table 3. Setting Boot Features Menu Setting Contents NumLock Set NumLock status at start-up ・On (Default) – ON ・Off - OFF QuickBoot Set QuickBoot ・Disabled - disable ・Enabled(Default) - enable BIOS Level USB Select USB support to reduce boot time. ・Disabled - disable ・Enabled(Default) - enable USB Legacy Select USB SMM support to use mouse, keyboard, mass storage by legacy OS like DOS.
BIOS Setup 8.2. Advanced Menu 8.2.1. Select Language Table 4. Setting Select Language Select Language Setting Contents Language can be selected ・English ・Japanese ・French ・Korean ・Chinese 8.2.2. ACPI Configuration Table 5. Setting ACPI Configuration Setting Contents FACP-RTC S4 Flag Value Set RTC S4 flag value of FACP table. (Only valid at ACPI) ・Disabled - disable ・Enabled(Default) - enable APIC-IO APIC Mode Enable APIC mode.
CPU-71-15 - User Manual 8.2.3. Processor Configuration 8.2.3.1. Processor Power Management Table 6. 設定 38 Processor Configuration Setting Contents Active Processor Cores Set number of cores to be active. ・All (Default)- active all cores ・[Number]-different for each processor core number. Intel(R) HT Technology Enable Hyper-Threading technology. When this is disabled, one thread will be active per active core.
BIOS Setup 8.2.3.2. Processor Power Management Table 7. Processor Power Management Setting Contents Setting Intel Speed Step (R) Set processor performance state (P state). ・Disabled - disable ・Enabled(Default) - enable Boot Performance mode Set performance mode for boot before handover to OS. ・Max Performance(Default) ・Max Battery ・Auto Turbo Mode Enable processor Turbo mode and EMTTM.
CPU-71-15 - User Manual Contents Setting Lock TDP setting Lock of TDP MSR_CONFIG_TDP_CONTROL. ・Disabled(Default) - disable ・Enabled - enable TDP Custom Setting Set custom TDP. ・Disabled(Default) - disable ・Enabled - enable C-States Enabling standby state (power saving states(C-States)) of processor. ・Disabled - disable ・Enabled(Default) - enable Extend C-States Enable P-States change combined with C-States status.
BIOS Setup 8.2.4. Peripheral Configuration Table 8. Peripheral Configuration Setting Contents Setting Spread Spectrum Clock Enable Spread Spectrum Clock. ・Disabled(Default) - disable ・Enabled - enable 8.2.5. HDD Configuration Table 9. Contents Setting SATA Device Set SATA device. ・Disabled - disable ・Enabled(Default) - enable Interface Combination Serial ATA port X Hot Plug HDD Configuration Setting *13 *13 External Port *13 Set operating mode of SATA controller.
CPU-71-15 - User Manual 8.2.6. Memory Configuration Table 10. Setting 42 Memory Configuration Setting Contents Memory Frequency Limiter Select maximum memory frequency (MHz). ・Auto (Default) ・1067 ・1333 ・1600 ・1867 ・2133 Max TOLUD Maximum value of TOLUD. If "Dynamic" is selected, TOLUD is set automatically based on maximum MMIO of installed graphic controller. ・Dynamic (Default) ・1 GB ・1.25 GB ・1.5 GB ・1.75 GB ・2 GB ・2.25 GB ・2.5 GB ・2.75 GB ・3 GB ・3.25 GB ・3.
BIOS Setup 8.2.7. System Agent (SA) Configuration 8.2.7.1. DMI Settings Table 11. DMI Setting Contents Setting DMI Link ASPM Control Enable SA ASPM (Active State Power Management) of DMI link. ・Disabled (Default) ・L0S ・L1 ・L0S and L1 ・Auto DMI Gen2 Support Control Enable SA ASPM (Active State Power Management) of DMI link. ・Disabled (Default) ・Enabled ・Auto 8.2.7.2. Intel (R) VT for Directed I/O (VT-d) Table 12.
CPU-71-15 - User Manual Setting 44 Contents DVMT Total Gfx Mem Set DVMT5.0 DVMT graphic memory size. Invalid when external graphics is connected. ・128MB (Default) ・256MB ・Max Render Standby Select IGD Render Standby property. ・Disabled ・Enabled (Default) IGD Thermal Control Set IGD thermal control. ・Disabled (Default) ・Enabled GT Turbo Mode Control Set GT Turbo Mode control. ・Disabled (Default) ・Enabled IGD – Boot Type Select video device activated during POST.
BIOS Setup Setting Contents GMCH BLC Control Select GMCH BLC control. ・PWM - Inverted (Default) ・GMBUS - Inverted ・PWM - Normal ・GMBUS - Normal BIA Select BIA. When [Auto] is selected, GMCH use VBT default. [Level n] set aggressive level. ・Disabled ・Level 1 ・Level 2 ・Level 3 ・Level 4 ・Level 5 ・Auto (Default) Spread Spectrum clock chip Set SSC. ・Off (Default) ・Hardware: SSC is set by chip ・Software: SSC is set by BIOS IGD – TV Control Set IGD - TV. Invalid when external graphics is connected.
CPU-71-15 - User Manual 8.2.7.4. PEG Port Configuration Table 14. Setting 46 PEG Port Configuration Setting Contents PEG 0 – Gen X Set PEG0 B0:D1:F0 link speed. ・Auto (Default) ・Gen1 ・Gen2 ・Gen3 PEG 1 – Gen X Set PEG1 B0:D1:F1 link speed. PEG 2 – Gen X Set PEG2 B0:D1:F2 link speed. PEG 3 – Gen X Set PEG3 B0:D6:F0 link speed. Always Enable PEG Enable always PEG. ・Disabled (Default) ・Enabled PEG ASPM Set PEG ASPM.
BIOS Setup 8.2.8. South Bridge Configuration Table 15. South Bridge Configuration Setting Contents Setting HPET Support Set HPET (High Precision Event Timer).When enabled, corresponding enable bit will be set by RSDT point HPET table. ・Disabled ・Enabled (Default) HPET Memory Map BAR Select HPET memory map BAR address. ・FED00000 (Default) ・FED01000 ・FED02000 ・FED03000 State After G3 Set the state which will be moved when power is back after G3 state.
CPU-71-15 - User Manual Contents Setting Gen3 Equalization Implementation of PEG Gen3 equalization procedure. ・Disabled ・Enabled (Default) Gen3 Root Port Preset Set Gen3 Equalization preset value for root port. ・1～11 (Default：8) Gen3 End Port Preset Set Gen3 equalization preset value for end port. ・0～10 (Default：7) PEG Sample Calibrate Set PEG sample calibrate. ・Disabled ・Enabled ・Auto (Default) PEG Gen3 Equalization Phase2 Implementation of PEG Gen3 equalization Phase2.
BIOS Setup 8.2.8.3. PCI Express Port 3～5 Configuration Table 18. PCI Express Port 3～5 Configuration Setting Contents Setting PCI Express Port 3～5 Set PCI Express Root Port. ・Disabled ・Enabled (Default) 8.2.8.4. SB USB Configuration Table 19. SB USB Configuration Setting Contents Setting EHCI1 Set USB ECHI (USB2.0). ・Disabled ・Enabled (Default) EHCI2 Set USB ECHI (USB2.0) function. ・Disabled ・Enabled (Default) USB Per-Port Disable Control Set USB per-Port (#0-5, #8, #9) Disable.
CPU-71-15 - User Manual 8.2.9. Network Configuration Table 21. Network Configuration Setting Contents Setting PCH Internal LAN Set PCH internal LAN. ・Disabled ・Enabled (Default) LAN OPROM Selection Wake on PCH LAN ASF Support *15 *15 Set PCH internal LAN used for minimum configuration of Quiet Boot. ・Disabled ・Enabled (Default) Set wake on PCH LAN. ・Disabled ・Enabled (Default) *15 Set alert specification form.
BIOS Setup 8.2.11. SMBIOS Event Log Table 44. SMBIOS Event Log Setting Setting Contents Event Log Enable/disable of event log. ・Disabled ・Enabled (Default) View SMBIOS event log Display of SMBIOS event log. ・Displays log with “Enter” Mark SMBIOS events as read Marking SMBIOS event as read. Marked SMBIOS event is not displayed. Clears SMBIOS events Clearing SMBIOS event. 8.2.12. ME Configuration Table 45. Setting ME Configuration Setting Contents Intel(R) ME Enable Intel(R) Management Engine.
CPU-71-15 - User Manual 8.2.13. Thermal Configuration Table 46.
BIOS Setup Contents Setting PCH Temp Read Enable *19 Set PCH temperature read. ・Disabled ・Enabled (Default) PCH Temp Read Enable *19 Set PCH temperature read. ・Disabled ・Enabled (Default) CPU Energy Read Enable CPU Temp Read Enable *19 CPU2 Temp Read Enable TS On DIMM Enable Alert Enable Lock *19 *19 *19 *19 ME SMBus Thermal Reporting Set CPU energy read. ・Disabled ・Enabled (Default) Set CPU temperature read. ・Disabled ・Enabled (Default) Set CPU 2 temperature read.
CPU-71-15 - User Manual 8.2.15. Intel Rapid Start Technology Table 48. Setting iRST Support Entry on S3 RTC wake Entry after Intel Rapid Start Technology Setting Contents Set iRST. ・Disabled (Default) ・Enabled *20 Entry on S3 RTC wake. ・Disabled ・Enabled (Default) *20 Enabling RTC boot timer when enter to S3.
BIOS Setup 8.5. Exit Menu Table 51. Setting Exit Menu Setting Contents Exit Saving Changes Exits the setup menu with saving all the changes same as F10, then resets the system automatically. Exit Discarding Changes Exits the setup menu without saving the change same as Esc, then resets the system automatically. Load Setup Defaults Loads the setup default value same as F9. Load Optimized Defaults Loads optimized defaults by boot time and system performance.
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