An0065 CPU-1450: Soft Power Management Rev. 1.
Table of Contents 2 Disclaimer The information in this manual has been carefully checked and is believed to be accurate. Eurotech assumes no responsibility for any infringements of patents or other rights of third parties, which may result from its use. Eurotech assumes no responsibility for any inaccuracies that may be contained in this document. Eurotech makes no commitment to update or keep current the information contained in this manual.
Table of Contents Conventions The following table lists conventions used throughout this guide. Warnings and Important Notices: Warning: Information to alert you to potential damage to a program, system or device or potential personal injury Information note: Indicates important features or instructions to observe An0065.
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Table of Contents Conventions ................................................................................................................................................... 3 Table of Contents ............................................................................................................................................ 5 Chapter 1 The Soft Power Management....................................................................................................
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Chapter 1 The Soft Power Management Soft Power Management (SPM) is a technique that allows users to put the CPU module into a low power mode (therefore decreasing power consumption) while keeping the capacity to restart work as soon as something happens. When the CPU-1450 module is powered off with SPM, just a little part of the board remains supplied. This part monitors the system inputs, looking for wake-up events.
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Chapter 2 CPU-1450 SPM block diagram architecture The CPU-1450 is a PC/104-Plus module realized with a mezzanine architecture approach and comprises of two modules: Celeron Processor Module PIII Carrier For better understanding of the Power Management functionality of the CPU-1450 we have shown the following block logic architecture that focuses on the chipset that manages the power saving functions. In the diagram the dotted lines show the previous block differences.
CPU-1450 SPM block diagram architecture 10 Low Voltage Intel Celeron Processor Intel 82815 GMCH IDE Ultra ATA PCI USB 4 port AC97 Processor Module Celeron PC133 SDRAM On Board 256MB +5V Intel 82801 ICH2 LTC1536 Ethernet 10/100Mb +3V3 PWROK PCI to ISA bridge PWRBTN# VGA LPC SLP_S3# SLP_S5# +5V +3V3 Serial 1 and 2 Parallel Port Keyboard Mouse ISA +5VSB +3V3SB National Instrument PC87364 Super IO PWBTOUT +5V JPR2 Default 1-2 +5VSB PWRBTN# J9 PWRBTN # PSON# RTC Carrier PIII Figure
CPU-1450 SPM block diagram architecture Intel 82801 ICH2 and System Power States Table 1 shows the power states defined for ICH2-based platforms, the state names generally match the corresponding ACPI states, the hardware implementation of the CPU-1450 assembly does not support the greyed areas listed in the following table: State/Sub-states G0/S0/C0 G0/S0/C1 G0/S0/C2 G1/S1 G1/S3 G1/S4 G2/S5 G3 Legacy Name / Description Full On: Processor operating. Individual devices may be shut down to save power.
CPU-1450 SPM block diagram architecture 12 System Power Planes The system has several independent power planes, as described in the following table. Note that when a particular power plane is shut off, it should go to a 0V level. Plane Controlled by MAIN SLP_S3# signal RESUME Always present Description When SLP_S3# goes active (low), power is shut off to any circuit not required to wake the system.
CPU-1450 SPM block diagram architecture Event Input Signals and Their Usage Transitions rules for ICH2: Present State G0/S0/C0 G0/S0/C1 G0/S0/C2 G0/S0/C3 (ICH2-M only) G1/S1, G1/S3, or G1/S4 G2/S5 Transition Trigger Processor halt instruction Level 2 Read Level 3 Read SLP_EN bit set Power Button Override Mechanical Off / Power Failure Any Enabled Break Event STPCLK# goes active Power Button Override Power Failure Any Enabled Break Event STPCLK# goes inactive and previously in C1 Power Button Overr
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Chapter 3 CPU-1450 Power management connections To access the Soft Power Management capabilities of the CPU-1450, specific connections need to be made; this chapter is intended to document the connections versus the wake-up devices and to supply the CPU1450 in a Power Management compliant mode.
CPU-1450 Power management connections 16 Ethernet The CPU-1450 J12 connector is used for the Ethernet connection during the Wake on LAN events. J12 Ethernet Figure 3. J12Connector Layout Table 5. J12 Connector pin out Pin # Signal 1 +3.3VSB 2 ACTIVITY LED 3 RX+ 4 RX- 5 LINK LED 6 GND 7 TX+ 8 TX- The Eurotech Ethernet Transceiver To establish an Ethernet connection an Ethernet Transceiver must be used.
CPU-1450 Power management connections Serial 1 & Serial 2 The CPU-1450 J8 connector is used for the Parallel, Serial 1 and Serial 2 ports. In the soft power management the Ring Indicator signal on the Serial sections can be used as a wake-up event. The signal level applied to the RI pins should be greater than 3V because this signal is applied to a GATE of a transistor that drives the RI pin of the ICH2. Furthermore, the high level must be applied using a current limiting resistor.
CPU-1450 Power management connections 18 Auxiliary Power Connector The CPU-1450 connector J9 is a 12-Pin (6x2) 2.54mm pitch connector and is used to power the module as an alternative to the PC/104-Plus bus, this connector also carries signals for power management J9 Auxiliary Power Figure 5. Pin # Signal J9 Connector layout Pin # Signal 1 GND 2 VDD 3 N.C. 4 +12v 5 -5V 6 -12V 7 GND 8 VDD 9 N.C.
CPU-1450 Power management connections Electrical connections In general if you want to supply the CPU-1450 with an ATX power supply here the connections you've to realize: Pin 1 2 3 4 5 6 7 8 9 10 11 12 Signal GND VDD (+5VDC) N.C. +12VDC N.C. -12VDC GND VDD (+5VDC) N.C. PWR_BTN +5VSB ATX ON J9 Aux PWR Description Ground +5V DC signal Not connected +12 VDC signal Not connected -12 VDC signal Ground +5 VDC signal Not connected Power Button Always high (ATX only) ATX Power on signal Table 7.
CPU-1450 Power management connections 20 Development Kit connections A good platform to experiment with the power saving capabilities is the Eurotech development kit; using this system you can minimize the number of power connections wired in a safe way over the motherboard. We suggest using the same reference colours listed in Table 8 with AWG18 wire.
Chapter 4 SPM Management The Soft Power Management capabilities of the CPU-1450 are integrated in the ICH2 82801 and the Super I/O PC87364. The CPU has the capability to be placed in a low-power operating mode where CPU activity is stopped and power consumption reduced. Operating in this mode is possible by supplying the CPU with the power supply architecture previously described.
SPM Management 22 Entering Low Power mode This chapter describes how to enter the low-power mode and the events that allow the user to wake-up the CPU-1450 from the sleep state. To minimize power consumption the CPU has to be placed into a low power consumption mode, this may be done via software.
SPM Management Wake-up events The hardware of the CPU-1450 has been developed to allow the user to manage the Soft Power Management modes with the following wake-up event sources: Serial Port Ring Indicator pin Ethernet External Power Button Wake on RTC All the possible wake-up events can be enabled or disabled by setting the Soft Power Enable Registers. The user can also know what event has occurred to turn-on the power by reading the Soft Power Status Registers.
SPM Management 24 External Power Button PWRBTN# A low signal in the Power Button pin (if enabled) can be used to turn-on or turn-off the system from the low power mode. A low level at this pin activates the wake-up functionality. Wake on RTC A hardware wake-up event from the sleeping state can be made at a predetermined time with an RTC alarm.
Chapter 5 Soft Power Management Registers The SPM register model consists of a number of fixed register blocks that perform designated functions. A register block consists of a number of registers that perform Status, Enable and Control Functions. Status bits are only set through some defined hardware events. Unless otherwise noted, Status bits are cleared by writing a HIGH to that bit position, and upon VTR POR. Writing 0 has no effect.
Soft Power Management Registers 26 Intel® 82801BA I/O Controller Hub 2 (ICH2) The following tables report the ICH2 registers useful for the power management. Name PMCSR PM1_STS Address PCI Configuration Register Bus 1, Device 8, Function 0, offset E0h I/O address 6000h PM1_EN I/O address 6002h PM1_CNT I/O address 6004h GPE0_EN I/O address 602Ah Table 9. Function Power Management Control/Status Register of LAN Controller. Used to enable PME and set Power State. Power Management 1 Status Register.
Soft Power Management Registers PM1_STS Power Management 1 Status Register I/O Address (ACPI PM1a_EVT_BLK) Attribute Default Value Size Lockable Usage Power Well 6000h R/WC 0000h 16-bit No ACPI or Legacy Bits 0–7: Core, Bits 8–15: Resume Except Bit 11 in RTC If bit 10 or 8 in this register is 1 and the corresponding _EN bit is set in the PM1_EN register, ICH2 generates a Wake Event.
Soft Power Management Registers 28 PM1_EN—Power Management 1 Enable Register I/O Address (ACPI PM1a_EVT_BLK) Attribute Default Value Size Lockable Usage Power Well Bit 15:11 10 8 5 0 6002h R/W 0000h 16-bit No ACPI or Legacy Bits 0–7: Bits 8–15: Core, Resume Description Reserved. RTC Event Enable (RTC_EN)—R/W. This bit is in the RTC well to allow an RTC event to wake after a power failure. This bit is not cleared by any reset other than RTCRST# or a Power Button Override event.
Soft Power Management Registers PM1_CNT—Power Management 1 Control Register I/O Address (ACPI PM1a_EVT_BLK) Attribute Default Value Size Lockable Usage Power Well Bit 13 12:10 2 1 0 6004h R/W 0000h 32-bit No ACPI or Legacy Bits 0–7: Bits 8–15: Core, Resume Description Sleep Enable (SLP_EN)—WO. Setting this bit causes the system to sequence into the Sleep state defined by the SLP_TYP field. Sleep Type (SLP_TYP)—R/W.
Soft Power Management Registers 30 GPE0_EN—General Purpose Event 0 Enables Register I/O Address (ACPI PM1a_EVT_BLK) Attribute Default Value Size Lockable Usage Power Well 602h R/W 0000h 16-bit No ACPI Bits 0–7: Bits 8–15: Core, RTC Note: This register is symmetrical to the General Purpose Event 0 Status Register. All the bits in this register should be cleared to 0 based on a Power Button Override. The resume well bits are all cleared by RSMRST#. The RTC sell bits are cleared by RTCRST#.
Soft Power Management Registers SuperIO National PC87364 The following tables show the National Super I/O PC87364 registers useful for the power management: Access to the Super I/O configuration registers is via an Index-Data register pair, using only two system I/O byte locations. The base address of this register pair is determined during reset, according to the state of the hardware strapping option on the BADDR pin. The following table shows the selected base addresses as a function of BADDR.
Soft Power Management Registers 32 Super I/O Configuration D Register (SIOCFD) Location Index Type Battery-backed register Name Configuration D Register Address Indexed 2Dh. Index/data pair register address is 2E/2Fh. Figure 7. Bit 7 2Dh Varies per bit 6 Function Power Management Control/Status Register. Used to set ACPI mode for Super I/O chip .
Chapter 6 Software examples In this section there are some programs useful to set the sleep modes. The examples are developed in DOS O.S. and compiled with Watcom C (see bibliography). We are going to analyse some examples that may be useful understanding the following Wake-up events: Wake On RTC Serial Port Ring Indicator pin Wake On LAN (Ethernet) These software examples are also contained in the “An0065_SW_Package” available in the download area @ www.eurotech.it (“Tools” section of the CPU-1450).
Software examples 34 Wake on RTC alarm We start with an example that doesn’t need additional external hardware. The following code will put the CPU module in soft-off sleep mode and wake it after 2 minutes using RTC alarm. #include #include #include /* Eurotech SpA /* Version 0.5, date 07-02-2006 */ void main() { printf( "Eurotech S.p.a.
Software examples Index 00h 01h 02h 03h 04h 05h 06h 07h Name Seconds Seconds Alarm Minutes Minutes Alarm Hours Hours Alarm Day of Week Day of Month Table 16. Index 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh–7Fh Name Month Year Register A Register B Register C Register D 114 Bytes of User RAM RTC (Standard) RAM Bank The I/O locations 70h and 71h are the standard ISA location for the real-time clock. An0065.
Software examples 36 Wake on Ring Indicator Pulse The following code will put the CPU module in soft-off sleep mode; then a positive voltage applied on serial port Ring Indicator pin will wake it. #include #include #include /* Eurotech SpA */ /* version 0.5 , date 07-02-2006 */ void main() { printf( "Eurotech S.p.a.
Software examples Wake on LAN (Ethernet) The following example shows the configuration procedure that enables a Wake-On-LAN wake-up event. 1. Verify that the Network peripheral is enabled in the BIOS. 2. Detect the MAC address of your CPU-1450 Ethernet adapter, this may be done using the DIAGS SW utility available from Intel or using the “An0065_SW_Package” available in the download area @ www.eurotech.it (“Tools” section of the CPU-1450). 3. Configure the register PMCSR of the Ethernet controller.
Software examples 38 5. To verify the Wake-On-LAN functionality now you need to send to the CPU a Magic Packet via Ethernet.
Chapter 7 CPU power consumption The main goal of Soft Power Management is to reduce CPU power consumption when not needed. This chapter compares the power consumption of a CPU-1450 with Celeron 400MHz and 256MB SDRAM running in standard mode and some sleep or low power modes. The following table list the CPU-1450 power consumption in the different states: CPU-1450 w/ Celeron 400MHz and 256MB SDRAM Power mode Ethernet connection Power consumption typical Full power mode Negligible 8.
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Chapter 8 Appendix
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Related Software Some software examples are contained in the “An0065_SW_Package” available in the download area @ www.eurotech.it (“Tools” section of the CPU-1450). Related Documents For more information please refer to the CPU-1450 user manual. http://www.eurotech.it Super I/O PC87364 www.national.com ICH2 82801 www.intel.com Open Watcom C++ http://www.openwatcom.org/index.php/Main_Page Ether-wake http://gsd.di.uminho.pt/jpo/software/wakeonlan/mini-howto/wol-mini-howto-3.
