User`s manual

Am186™CC Microcontroller Router Reference Design Users Manual
2-27
Using HDLC channel D for Am186CC microcontroller-to-DSLAC
communication causes the Low-Speed UART to be non-functional (the High-
Speed UART is functional). The HDLC channel D pins are multiplexed with the
UART. The High-Speed UART flow control is also unavailable because the HDLC
channel D time-slot control is multiplexed with one of these pins. The UART flow
control signals (channel C) are used for the High-Speed UART.
RSLIC Interface
NOTE: See sheets 7, 8, and 9 in the schematics for DSLAC and RSLIC circuitry.
The DSLAC device provides a direct connection to the Am79R79 RSLIC through
two sets of data and control I/O signals used for each channel. The data signals are
analog signals from the RSLIC device. These analog signals are digitized and
transmitted to the PCM bus. The control signals are used to control telephone states
and to detect status.
The RSLIC device ringing is generated via a 20-Hz, CMOS-compatible signal.
The signal is created using U3D and U3C from the Am186CC microcontroller’s
PIO40 and PIO41 signals, which correspond to POTS channels 1 and 2,
respectively. The inverter takes the 3.3-V, peak-to-peak PIO outputs and converts
them to 5-V peak-to-peak to satisfy the requirements for the RSLIC device.
Dual Tone Multiple Frequency (DTMF)
NOTE: See sheet 9 in the schematics for the DTMF circuitry.
The two DTMF receivers are used to detect valid tone pairs from each POTS
telephone interface, and then translate them into digital signaling. The digital
signaling is used by the Am186CC microcontroller to set up and place a call. When
a DTMF detects a valid tone pair from the RSLIC device, the DTMF sends an
active High interrupt (INT4 for POTS channel 1 and INT5 for POTS channel 2)
to the Am186CC microcontroller. The DTMF becomes available on AD3–AD0
after the Am186CC microcontroller issues an active High output enable to the
corresponding DTMF OE pin. The output enables are generated by inverting PCS5
and PCS4
for POTS channels 1 and 2, respectively, in the PLD (U43 at location
E-5).
about.book Page 27 Wednesday, July 21, 1999 11:10 AM