User`s manual

Am186™CC Microcontroller Router Reference Design User’s Manual
2-19
ISDN S/T Interface
NOTE: See sheet 5 in the schematics for the ISDN S/T interface circuitry.
The glueless connection between the Am186CC microcontroller and the
Am79C32A ISDN DSC provides the four-wire 2B+D S/T interface. The DSC
serial interface is capable of being configured as an IOM-2 or SBP serial
microprocessor interface. This interface is used to transfer data to and from the
Am186CC microcontroller using the microcontroller’s integrated HDLC in GCI
or PCM mode; I/O cycles via the address and data bus for AM79C32A
initialization.
The Am186CC microcontroller provides a full-duplex path between the TE and
NT device or the PABX linecard. It processes the ISDN BRI bit stream, which
consists of two 64-Kbit/s B channels and a single 16-Kbit/s D channel. The four-
wire ISDN S/T interface is first directed through line filtering devices that isolate
and protect the modem from the outside lines.
In the default S/T configuration, the Am79C32A DSC is operating in SBP mode.
The Am79C32A DSC is also providing the clock and frame sync to the Am186CC
microcontroller across the integrated HDLC A interface, which is configured in
PCM mode, and to the Am79C031 DSLAC device (PCM codec) used for the POTS
interface.
An alternate configuration uses the Am79C32A DSC in an IOM-2 mode. The
Am186CC microcontroller provides a GCI-to-PCM (pulse code modulation)
conversion of the data clock and frame sync to enable the Am79C031 DSLAC
device (PCM codec), to communicate directly between the Am79C32A DSC and
the Am79C031 codec for the POTS interface. See “POTS Interface” on page 2-25
for more information about this configuration.
The Am79C32A DSC uses the PCS1
(peripheral chip select 1) signal, which asserts
between addresses 100h and 1FFh, and the INT6 (interrupt 6) signal, which is edge-
triggered as an active Low interrupt. The Am79C32A DSC MCLK signal is set to
12.288 MHz. The PAL (U43 at location E-4) divides it by 3 to provide the
4.096 MHz used to drive the MCLK input to the Am79C031 DSLAC device on
the POTS interface. The PAL (U43 at location E-4) is used to synchronize MCLK
and PCLK for the DSLAC. See “DSLAC PCM Interface” on page 2-25.
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