User`s manual

Am186™CC Microcontroller Router Reference Design User’s Manual
2-17
The Ethernet controller is a bus mastering device and DMAs directly to packet
buffer memory space. The Ethernet controller supports DMA to SRAM, not
DRAM. Because main system memory is DRAM, the 64K x 16 SRAM must be
used as packet buffer memory.
A small amount of glue logic is required to interface the PCnet-ISA II Ethernet
controller to the Am186CC microcontroller because the PCnet-ISA II Ethernet
controller is an ISA peripheral device. The logic is implemented using discrete
devices: U3F (D-9), U47A (I-6) and U48A (E-5). See sheet 3 of the schematics
for details. The logic controls two signals between the Ethernet controller and the
Am186CC microcontroller: SR_CE
and BHLDA.
U48A creates the Ethernet packet SRAM chip select, SRAM_CE
, from the
MASTER
output when the PCnet-ISA II Ethernet controller is the bus master.
When the Am186CC microcontroller is the bus master, the SRAM_CE
output is
three-stated and MCS0
is used as the packet SRAM chip select.
BHLDA
is an inverted Am186CC microcontroller HLDA and becomes the
PCnet-ISA II DMA acknowledge input (DACK
). Refer to U3F, U47A, and U48A
on sheet 3 of the schematics.
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