User`s manual

Am186™CC Microcontroller Router Reference Design User’s Manual
2-13
System Memory
The Am186CC microcontroller router reference design uses DRAM and Flash
memory for system memory. Figure 2-3 shows the DRAM and Flash memory map.
A small SRAM device is also used as an Ethernet packet buffer.
Figure 2-3. DRAM and Flash Memory Map
DRAM/SRAM Memory
NOTE: See sheet 4 in the schematics for the DRAM and SRAM circuitry.
A 256K x 16 EDO, 40-ns DRAM allows zero wait state operation at up to 50 MHz.
The DRAM resides in the lower 512 Kbyte of LCS
memory space (0h–7FFFFh).
The Am186CC microcontroller provides the DRAM memory address on the odd
Am186CC microcontroller addresses A1–A17 to provide a direct connection to
the DRAM device. The DRAM RAS
and CAS signaling is provided on the
LCS0
/RAS0, MCS1/CAS1, and MCS2/CAS0 signals from the Am186CC
microcontroller.
The Am186CC microcontroller router reference design is populated with a
64K x 16, 35-ns TSOP II SRAM device used as shared memory (shared by the
system and by the Ethernet controller). The Am186CC uses MCS0
to select the
SRAM. The SRAM can be mapped into memory space at various addresses
(mapping SRAM to 80000h is common). The space the SRAM resides in can be
moved from 00000h up to FFFFFh in increments equal to the SRAM block size.
There is no fixed location for the SRAM as it is chosen by the programmer.
FFFFFh
00000h
DRAM Memory
Flash Memory
80000h
7FFFFh
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