User`s manual
Am186
TM
CC Microcontroller ISDN TA Reference Design Manual
A-14
1
1
2
2
3
3
4
4
5
5
E E
D D
C C
B B
A A
121
80
AM186CC
1 120
41
160
8140
[RAS0#]
[CAS1#]
[CAS0#]
[UDMNS]
[UDPLS]
NOTE: Decoupling
capacitors each located
next to a VCC pin
REV 2.0: Test points removed
REV 2.0: Added
REV 2.0: Added
PROCESSOR.SCH
1.0
(C) Advanced Micro Devices, Inc. (800) 222-9323
5204 E. Ben White Blvd.
Austin, TX 78741
AMD Proprietary/All Rights Reserved
26Friday, August 14, 1998
Design Name
Size Schematic Sheet Name Rev
Date: Sheet of
16x12.5
VCCA
INT6
VCC
INT_TERM
AD2
AD8
AD14
AD7
AD1
AD12
AD6
AD11
AD10
AD0
AD3
AD4
AD5
AD13
AD15
AD9
CCWHBR
CCALER
CCDTRR
CCDENR
CCBHER
CCS0R
CCS1R
CCS6R
CCBSIZER
CCQS0R
CCQS1R
MA2
MA15
MA12
MA5
MA6
MA17
MA13
MA19
MA4
MA10
MA0
MA9
MA16
MA7
MA11
MA14
MA3
MA18
MA8
MA1
CCMAR0
CCMAR1
CCMAR2
CCMAR3
CCMAR4
CCMAR5
CCMAR6
CCMAR7
CCMAR8
CCMAR9
CCMAR10
CCMAR11
CCMAR12
CCMAR13
CCMAR14
CCMAR15
CCMAR16
CCMAR17
CCMAR18
CCMAR19
CCUCSR
CCLCSR
CCMCS0R
CCMCS1R
CCMCS2R
CCRDR
CCWRR
CCWLBR
CCS2R
VCC
VCC3
VCCA
VCC3
VCC3
INT_TERM
FB1
MURATA BLM31P500SPB
+
C1
3.3uF
16V
B-CASE
C3
0.01uF
C15
0.01uF
C4
0.1uF
C5
0.1uF
C6
0.1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
C10
0.1uF
C11
0.1uF
C12
0.1uF
C13
0.1uF
C61
0.1uF
C62
0.1uF
C63
0.1uF
C64
0.1uF
C65
0.1uF
C66
0.1uF
U1
AM186CC
1
21
33
41
53
61
72
71
83
100
82
108
121
130
140
155
22
60
73
74
75
76
12
27
40
48
59
68
77
78
91
30
31
32
36
37
42
43
44
45
49
50
64
65
69
70
84
85
88
89
90
28
29
34
35
38
39
46
47
51
52
66
67
86
87
92
93
105
107
109
110
111
112
113
115
124
145
146
147
2
3
4
54
55
56
57
58
62
63
94
114
116
117
118
119
122
123
134
135
136
137
138
139
149
150
151
152
153
154
156
157
158
15914
15
98
99
141
142
143
144
126
127
128
129
131
132
5
6
7
8
9
10
11
13
16
95
96
97
17
18
19
20
101
102
103
104
80
81
23
24
25
26
106
120
125
133
148
160
79
VSS
VSS
VSS
VSS
VSS
VSS
VSSA
VSS
VSS
VSS
VSSUSB
VSS
VSS
VSS
VSS
VSS
UCLK [USBSOF] [USBSCI] [PIO21]
CLKOUT
X1
X2
USBX1
USBX2
VCC
VCC
VCC
VCC
VCC
VCC
VCCA
VCC
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
AD0
AD8
AD1
AD9
AD2
AD10
AD3
AD11
AD4
AD12
AD5
AD13
AD6
AD14
AD7
AD15
DRQ1
INT0
INT1
INT2
INT3
INT4
INT5
NMI
DRQ0 [PIO9]
INT6 [PIO19]
INT7 [PIO7]
INT8 [PWD] [PIO6]
SDEN [PIO10]
SCLK [PIO11]
SDATA [PIO12]
S6
S2#
S1#
S0# {USBXCVR#}
RESOUT
QS0
QS1
BSIZE8#
RES#
TCLKA [FSCA] [FSCA]
RCLKA [DCLA] [CLKA]
RXDA [DDA] [RXDA]
TXDA [DUA] [TXDA]
RTRA# [PIO18]
CTSA# [TSCA#] [PIO17]
TCLKB [FSCB] [PIO41]
RCLKB [CLKB] [PIO40]
RTRB# [PIO39]
CTSB# [TSCB#] [PIO38]
RXDB [RXDB] [PIO36]
TXDB [TXDB] [PIO37]
TCLKC [FSCC] [PIO23]
RCLKC [CLKC] [PIO22]
RTRC# [PIO45]
CTSC# [TSCC#] [PIO44]
RXDC [RXDC] [PIO42]
TXDC [TXDC] [PIO43]
RTRU# [RCLKD] [CLKD] [PIO25]
CTSU# [TCLKD] [FSCD] [PIO24]
RXDU [RXDD] [RXDD] [PIO26]
TXDU [TXDD] [TXDD] [PIO20]ARDY [PIO8]
SRDY [PIO35]
HLDA {CLKSEL1}
HOLD
TMROUT0 [PIO28]
TMRIN0 [PIO27]
TMROUT1 [PIO1]
TMRIN1 [PIO0]
MCS0# {UCSX8#} [PIO4]
MCS1# [CAS1#]
MCS2# [CAS0#]
MCS3# [RAS1#] [PIO5]
LCS# [RAS0#]
UCS# {ONCE#}
PCS0# {USBSEL1} [PIO13]
PCS1# {USBSEL2} [PIO14]
PCS2#
PCS3#
PCS4# {CLKSEL2} [PIO3]
PCS5# {TESTMODE#} [PIO2]
PCS6# [PIO32]
PCS7# [PIO31]
WR# {PRODTST#} [PIO15]
WHB#
WLB#
RD#
DT/R# [PIO29]
DEN# [DS#] [PIO30]
ALE [PIO33]
BHE# {ADEN#} [PIO34]
RSRVD4 [UTXDPLS]
RSRVD3 [UTXDMNS]
RSRVD2 [UXVEN#]
RSRVD1 [UXVRCV]
USBD- [UDMNS]
USBD+ [UDPLS]
RTRHU# [RTRD#] [PIO47]
CTSHU# [CTSD#] [TSCD#] PIO46]
RXDHU [PIO16]
TXDHU
VCC
VCC
VCC
VCC
VCC
VCC
VCCUSB
R84 10K
R87 10K
R89 10K
R91 10K
R93 10K
R94 10K
R95 10K
R97 10K
R98 10K
R99 10K
R100 10K
R1 10K
R45 10K
R46 10K
R47 10K
R48 10K
R49 10K
R50 10K
R65 56
R67 56
R68 56
R69 56
R70 56
R71 56
R72 56
R73 56
R74 56
R75 56
R76 56
R77 56
R79 56
R81 56
R83 56
R85 56
R86 56
R88 56
R90 56
R92 56
R96 56
R61 56
R62 56
R63 56
R64 56
R66 56
R78 56
R80 56
R82 56
R51 10
C2
1000pF
C14
1000pF
LCS#
UCS#
MCS1#
RD#
WR#
MCS2#
MA[0..19]
AD[0 ..15]
PIO28
INT2
PIO39
PIO1
USBX1
FSCA
PIO31
TXDHU
PIO43
MCS0#
RXDHU
SDATA
PIO42
USBD+
SCLK
RXDA
TXDA
RTRHU#
X1
INT1
USBD-
X2
CLKA
PCS1#
CTSHU#
RESOUT
RES#
WLB#
INT7
INT8
INT0
PIO8
S2#
PIO35
PCS3#
PIO32
PIO18
about.book Page 14 Friday, December 18, 1998 9:41 AM