User`s manual

Am186
TM
CC Microcontroller ISDN TA Reference Design Manual
2-7
System Memory
This design uses 512 Kbyte of AMD Flash memory for code space located from
0x80000h–0xFFFFFh, and 512 Kbyte of DRAM. The memory schematic is shown
in Figure 2-4. The Am29F400 Flash memory is used in a 256k x 16 configuration.
The Am29F400 is byte/word selectable using the BYTE# pin. In case the
512 Kbyte of Flash memory is not sufficient, PIO 35 is routed to the chip to act as
a bank select. This allows drop in compatibility for larger Flash memory, such as
the 29F800 device.
Figure 2-4. ISDN TA System Memory
DRAM was chosen over SRAM as main memory in this application because
DRAM is more cost effective than SRAM and because the ISDN TA reference
design has an integrated DRAM controller that makes a glueless DRAM interface
simple to use. The Am186CC communications controller DRAM interface allows
zero-wait state operation at 48 MHz using a 40-ns DRAM. This DRAM device is
located from 0x00000h–0x7FFFFFh in low memory space and is selected using
LCS/RAS0.
256Kx16 DRAM Device 256Kx16 FLASH Device
[RAS0#]
[CAS0#]
[RD#]
[WR#]
[CAS1#]
MA5
MA11
MA3
MA1
MA9
MA17
MA7
MA15
MA13
FLASH_UCS#
BYTE#
MA17
MA16
MA12
MA3
MA10
MA8
MA2
MA9
MA11
MA15
MA13
MA4
MA14
MA1
MA5
MA7
MA6
MA18
AD8
AD7
AD4
AD12
AD13
AD11
AD15
AD10
AD1
AD7
AD10
AD2
AD4
AD9
AD11
AD3
AD6
AD3
AD8
AD0
AD13
AD12
AD14
AD1
AD6
AD0
AD14
AD5 AD5
AD2
AD15
AD9
VCC5
VCC5
VCC5
U2
V53C16258H SOJ
Mosel Vitelic V53C16258HK40
11
12
16
17
18
19
22
23
24
25
26
30
15
2
3
4
5
7
8
9
10
31
32
33
34
36
37
38
39
20
1
6
21
35
40
27
29
28
14
13
NC
NC
A0
A1
A2
A3
A4
A5
A6
A7
A8
NC
NC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VCC
VCC
VCC
VSS
VSS
VSS
OE#
LCAS#
UCAS#
RAS#
WR#
JP1
FLASH JP
1
2
U3
AM29F400 TSOP
31
33
35
38
40
42
44
32
34
36
39
41
43
17
9
25
24
29
30
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
10
45
13
37
14
16
46
27
26
11
28
12
15
47
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
A17
NC
A0
A1
DQ0
DQ8
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
NC
DQ15/A-1
NC
VCC
NC
NC
VSS
VSS
CE#
WE#
OE#
RESET#
RY/BY#
BYTE#
R6 *0
R4
10K
R5
10K
AD[0..15]
MCS2#
MCS1#
RD#
WR#
RES#
LCS#
MA [0..19]
UCS#
PIO31
PIO35
about.book Page 7 Friday, December 18, 1998 9:41 AM