Installation guide

Determining Component Status
5-22 Fault Tolerant System Administration (R1004H) HP-UX version 11.00.03
Figure 5-8 illustrates the logical CPU/memory configuration.
Figure 5-8. Logical CPU/Memory Configuration
The following sample ftsmaint ls output shows the logical hardware paths for
a twin CPU/memory system:
Modelx H/W Path Description State Serial# PRev Status FCode Fct
===========================================================================
- 15 LMERC Nexus CLAIM - - Online - 0
- 15/0/0 Processor CLAIM - - Online - 0
- 15/0/1 Processor CLAIM - - Online - 0
- 15/1/0 Memory CLAIM - - Online - 0
- 15/2/0 console CLAIM - - Online - 0
- 15/2/1 tty1 CLAIM - - Online - 0
- 15/2/2 tty2 CLAIM - - Online - 0
A CPU does not have an associated device node, but memory does have associated
nodes, /dev/phmem0 and /dev/phmem1, which correspond to the memory on
each CPU/memory board. Nodes for the three ports on a console controller are
/dev/console, /dev/tty1, and /dev/tty2.
Determining Component Status
The current status of a hardware component derives from the following two
sources:
A software state indicates how the system sees that component.
A hardware status indicates how the component is operating.
Main System Bus
GBUS
11
12
13
14
15
RECCBUS
0
1
CDIO
CAB
LNM
LSM
LMERC
transparent
0
Processor
0
Processor
1
15/0/0
15/0/1
transparent
1
Memory
0
15/1/0
transparent
2
console
0
tty1
1
tty2
2
15/2/0 15/2/1 15/2/2