Service manual

Schematic Diagrams
B - 4 Processor 2/7
B.Schematic Diagrams
Processor 2/7
PROCESSOR 2/7 ( CLK,MISC,JTAG )
R1 1 5
*1.1K_1%_04
D03C R121 change 750 ohm, R115 NC
+1.5S_CPU
R1 2 1
750_1%_04
D03C add R554
R5 5 4
1. 5 K _ 1 % _0 4
DR AMP W RG D_ CPU
VDDP WRGOOD_R
DDR3 Compensation Signals
Processor Compensation Signals
1. 5V
R56 6
*1 . 1 K_ 1% _ 0 4
Processor Pullups
Signal from PCH to Processor
Connect to PCH (PLT_RST#)
(needs to be level translated
from 3.3 V to 1.1 V).
XDP_PR EQ#
XDP_PR DY #
Connect to the Processor (VTTPWRGOOD) VTT_1.1 VR power
good signal to processor. Signal voltage level is 1.1
V.
If PROCHOT# is not used, then it must be terminated
with a 50-O pull-up resistor to VTT_1.1 rail.
FOR XDP
H_ CP URS T#
R549 0_04
3.3V 2,11,12,13, 15,16,18,21,24,26,27,28,29,34,36,37,38,41
R548 0_04
H_ PRO CH OT# _ D
R410 * 1K_04
3.3VS
H_DBR#_R
XDP_T DI_M
XDP _TR ST#
D03 ADD R548,R549 & DEL
CLK_DP_N/P
H_CPURST#
H_PR OC HO T#39
H_COMP3
H_COMP2
H_COMP1
H_COMP0
R 4 08 * 6 8 _ 04
D03 ADD
R537
1.1VS_PWR GD13,36
R 4 5 3 * 1 2 . 4K _ 1 % _ 04
D03 ADD
C685,C686,C687
R397 *51_04
R403 *51_04
R1 4 6 10 K_ 0 4
R131 1.5K_1% _04
R4 3 2 0 _ 04
R 425 49. 9_1% _04
R 4 11 2 0_ 1 % _ 04
R 110 0_04
Q3 8
MTN 7002ZHS3
G
DS
R4 4 9 0 _ 04
R 490 24.9_1%_04
R 404 49. 9_1% _04
R 398 51_04
R400 *51_04
R4 3 9 10 K_ 0 4
CLOCKS
MISC THERMAL
PWR MANAGEMENT
DDR3 MIS C
JTAG & BPM
U3 4 B
M O LE X 4 7 9 89 0 1 42
SM _ RC OM P[1]
AM1
SM _ RC OM P[2]
AN1
SM_DR AMR ST#
F6
SM _ RC OM P[0]
AL1
BC LK#
B16
BC LK
A16
BCLK_ ITP#
AT30
B CLK_ITP
AR30
PEG _C LK#
D1 6
PEG_C LK
E16
DPLL_REF_SSC LK#
A17
DPLL_REF_SSC LK
A18
CATERR#
AK14
COMP3
AT23
PECI
AT15
PROCHOT#
AN 26
TH ERM TR IP#
AK15
R ESET_OBS#
AP26
VCCP WRGOOD_1
AN 14
VCCP WRGOOD_0
AN 27
SM_DRAMPW ROK
AK13
V TT PW R GO OD
AM 15
RSTIN#
AL14
PM _ EXT_TS#[0]
AN15
PM _ EXT_TS#[1]
AP15
PR DY #
AT28
PREQ #
AP27
TCK
AN28
TMS
AP28
TR S T #
AT27
TDI
AT29
TDO
AR27
TDI_M
AR29
TD O _ M
AP29
DBR #
AN25
BPM # [0]
AJ 22
BPM # [1]
AK22
BPM # [2]
AK24
BPM # [3]
AJ 24
BPM # [4]
AJ 25
BPM # [5]
AH22
BPM # [6]
AK23
BPM # [7]
AH23
COMP2
AT24
PM_SYNC
AL15
TAPPW RG OO D
AM 26
COMP1
G16
COMP0
AT26
SKTOCC#
AH 24
R109 68_04
R 4 13 2 0_ 1 % _ 04
R558
10K_04
R1 3 5 * 0_ 0 4
R 493 100_1%_04
R12 5
750_1%_04
R 132 49. 9_1% _04
R 402 51_04
R399 *51_04
R 487 130_1%_04
XDP _TM S
3.3V
1.1VS_VTT
1.1VS_VTT
3.3V
1.1VS_VTT
BC LK_C PU_P 16
H_CPUPWRGD16
BC LK_C PU_N 16
BUF_PL T_R ST#12,15,25,26,27,29
H_ VT TPW RG D13
PM _ DR AM_ PW R GD13
C LK _EXP_ N 12
H _TH RMTR IP#16
C LK _EXP_ P 12
1.1V S_V TT 5,6,16,17,18,38
T S #_ D I M M 0_ 1 9 , 1 0
PM_ EXTTS#_ EC 25
H_PEC I16,25
3 .3V S 9 ,1 0,1 1 ,1 2, 13 ,1 5 ,16 ,1 7 ,1 8,2 0 ,2 1 ,22 ,2 3 ,24 ,2 5 ,2 6,2 7 ,2 8 ,29 ,3 0 ,3 1,3 2 ,3 3, 34 ,3 9
D ELAY_ PW R GD13,39
H_ PM_S Y NC13
+1. 5S_C PU
Q3 4 MTN 700 2ZHS3
G
D S
R555
1K_04
R559
100K_04
R 5 56 * 0 _0 4
R5 6 0 0 _ 04
DDR3_DRAMRST#9, 1 0
DDR 3 _D RAM RS T#
1.5V
CP U_ DR A MR ST#
D RAM RST_CN TR L_PC H16
C6 9 1
47n_10V_X7R _04
DRAMRST_CNTRL8
PM _E XTTS# [0 ]
U3 8
74 A H C 1 G 0 8 G W
1
2
5
4
3
D RAM PW RG D_ CP U
Q39
2N3904
B
E C
C 6 85 0 . 1u _ 1 0V _X 7 R _ 0 4
H_PR OCH OT# _ D
C 6 87 0 . 1u _ 1 0V _X 7 R _ 0 4
C 6 86 0 . 1u _ 1 0V _X 7 R _ 0 4
R1 4 1 0 _ 04
R4 4 3 0 _ 04
R514 *10m il_short
XDP_TDO _M
H_ PW R GD_ X DP
B C LK _I T P _ P
XDP_O BS0_R
PLT_RS T#_R
XDP_TCL K
PM _E XTTS# [1 ]
XDP_TRS T#
XDP_TMS
H_ CO MP3
SYS_AG ENT_PW RO K
XDP_O BS1_R
H_ CO MP2
XDP_O BS2_R
H_ CO MP1
XDP_O BS3_R
PLT_ R ST#1 5 ,2 4 ,28 ,4 1
XDP_O BS4_R
R 407 *1K_04
+1.5 S_ CPU _PW RG D 37
B C LK _I T P _ N
C PU_ DR A M RST #
XDP_O BS5_R
XDP _TD O_M
SM _R CO MP_ 0
XDP_O BS6_R
XDP_O BS7_R
SM _R CO MP_ 1
XDP _TD I_R
VDD PWRGOOD_R
SM _R CO MP_ 2
H_ CAT ER R#
XDP _PR EQ #
XDP _TC LK
XDP_TDI_R
XDP_TDO _R
H_ CO MP0
XDP_TDI_M
+1.5S_C PU 6,34
XDP_T DO _M
1.5V 9,10,18,28, 34,37,41
D03C
D03C
D03C
3.3V
C 690 0. 1u_10V_X7R_04
R5 5 3
10K_04
SM_RC OM P_0
SM_RC OM P_1
SM_RC OM P_2
R537 0_04
H_CA TER R#
D04 add R566
Sheet 3 of 57
Processor 2/7