Service manual

Schematic Diagrams
Processor 1/7 B - 3
B.Schematic Diagrams
Processor 1/7
C566 .1U_10V_X7R_04
C563 .1U_10V_X7R_04
C568 .1U_10V_X7R_04
C542 .1U_10V_X7R_04
C544 .1U_10V_X7R_04
C556 .1U_10V_X7R_04
C548 .1U_10V_X7R_04
C546 .1U_10V_X7R_04
C552 .1U_10V_X7R_04
C550 .1U_10V_X7R_04
C554 .1U_10V_X7R_04
C536 .1U_10V_X7R_04
C533 .1U_10V_X7R_04
C560 .1U_10V_X7R_04
C558 .1U_10V_X7R_04
C539 .1U_10V_X7R_04
C545 .1U_10V_X7R_04
C562 .1U_10V_X7R_04
C549 .1U_10V_X7R_04
C538 .1U_10V_X7R_04
C547 .1U_10V_X7R_04
C532 .1U_10V_X7R_04
C567 .1U_10V_X7R_04
C543 .1U_10V_X7R_04
C557 .1U_10V_X7R_04
C541 .1U_10V_X7R_04
C559 .1U_10V_X7R_04
C555 .1U_10V_X7R_04
C551 .1U_10V_X7R_04
C553 .1U_10V_X7R_04
C535 .1U_10V_X7R_04
C565 .1U_10V_X7R_04
PEG _R XN0
PEG _R XN1
PEG _R XN2
PEG _R XN3
PEG _R XN4
PEG _R XN5
PEG _TXP7
PEG _TXP2
PEG _TXP1
PEG _TXP15
CP U_THER M 2 5
PEG _TXN7
PEG _TXP12
PEG _TXP0
PEG _TXN6
PEG _TXP11
PEG _TXN1
PEG _R XN6
PEG _TXN14
PEG _TXN13
PEG _TXP4
PEG _TXP6
PEG _TXP9
PEG _TXN15
PEG _TXN0
PEG _TXP3
PEG _TXP14
PEG _TXN2
PEG _TXP10
PEG _TXN4
PEG _TXN12
PEG _TXN8
PEG _TXN11
PEG _TXP5
PEG _TXP8
PEG _TXN9
PEG _TXP13
PEG _TXN5
PEG _R XN7
PEG _TXN3
PEG _TXN10
3.3V3,11,12,13,15,16,18,21,24,26,27,28, 29,34,36,37,38,41
VD D311,25,27, 28,29,30,34,35,40
PEG _R XN8
PEG _R XN9
D02 BOM DEL
PEG _R XN1 1
PEG _R XN1 2
PEG _R XN1 3
PEG _R XN1 4
PEG _R XN1 5
PEG _R XP0
PEG _R XP1
PEG _R XP2
PEG _R XP3
PEG _R XP4
PEG _R XP5
PEG _R XP6
PEG _R XP7
PEG _R XP8
PEG _R XP9
PEG _R XP10
PEG _R XP11
PEG _R XP12
PEG _R XP13
PEG _R XP14
RN 9
1K_8P4R_04
81
72
6
5
3
4
PEG _R XP15
PEG_ R X#_ 4
PEG_ R X_1 4
PEG_ R X#_ 3
PEG_ R X#_ 5
PEG_ R X_2
PEG_ R X#_ 1 2
PEG_ R X_1 5
PEG_ R X_7
PEG_ R X#_ 0
PEG_ R X#_ 6
PEG_ R X_1 2
PEG_ R X_8
PEG_ R X#_ 1 5
PEG_ R X_1 1
PEG_ R X#_ 8
PEG_ R X_3
PEG_ R X#_ 1 4
PEG_ R X_9
PEG_ R X#_ 1 3
PEG_ R X#_ 9
PEG_ R X#_ 2
PEG_ R X_1
PEG_ R X_1 3
PEG_ R X_0
PEG_ R X#_ 1 0
PEG_ R X_1 0
PEG_ R X#_ 1
PEG_ R X_6
PEG_ R X_5
PEG_ R X#_ 7
PEG_ R X_4
PEG_ R X#_ 1 1
P E G _I R C O M P _R
EXP_RBIA S
PE G_ T XP[0 ..1 5 ] 2 4
PE G_ T XN [0 ..15 ] 2 4
6-86-27989-001
PEG _R X N[0 ..1 5]
PEG _R XP[0. .15 ]
PEG _T XN[0..15 ]
PEG _T XP[0..15]
P EG_RXP[0..15] 24
PEG _RXN[0..15] 24
PEG _R XN1 0
C19 .1U_10V_X7R_04
C35 .1U_10V_X7R_04
R 412 750_1%_04
C16 .1U_10V_X7R_04
C17 .1U_10V_X7R_04
C30 .1U_10V_X7R_04
R 409 49.9_1% _04
C14 .1U_10V_X7R_04
C46 .1U_10V_X7R_04
C44 .1U_10V_X7R_04
C29 .1U_10V_X7R_04
C45 .1U_10V_X7R_04
C26 .1U_10V_X7R_04
C40 .1U_10V_X7R_04
C41 .1U_10V_X7R_04
C24 .1U_10V_X7R_04
C643
*0.1u_16V_Y5V_04
C23 .1U_10V_X7R_04
C22 .1U_10V_X7R_04
C20 .1U_10V_X7R_04
C21 .1U_10V_X7R_04
C36 .1U_10V_X7R_04
C34 .1U_10V_X7R_04
C33 .1U_10V_X7R_04
C18 .1U_10V_X7R_04
C31 .1U_10V_X7R_04
C15 .1U_10V_X7R_04
PCI EXPRESS -- GRAPHICS
DMI Intel(R) FDI
U3 4 A
MO LE X 479890142
DMI _R X#[0]
A24
DMI _R X#[1]
C23
DMI _R X#[2]
B22
DMI _R X#[3]
A21
DMI _R X[0]
B24
DMI _R X[1]
D23
DMI _R X[2]
B23
DMI _R X[3]
A22
DMI _TX# [0]
D24
DMI _TX# [1]
G24
DMI _TX# [2]
F23
DMI _TX# [3]
H23
DMI _TX[0 ]
D25
DMI _TX[1 ]
F24
DMI _TX[3 ]
G23
DMI _TX[2 ]
E23
FDI_TX#[0]
E22
FDI_TX#[1]
D21
FDI_TX#[2]
D19
FDI_TX#[3]
D18
FDI_TX#[4]
G21
FDI_TX#[5]
E19
FDI_TX#[6]
F21
FDI_TX#[7]
G18
FDI_TX[ 0]
D22
FDI_TX[ 1]
C21
FDI_TX[ 2]
D20
FDI_TX[ 3]
C18
FDI_TX[ 4]
G22
FDI_TX[ 5]
E20
FDI_TX[ 6]
F20
FDI_TX[ 7]
G19
FDI_FSY NC [0]
F17
FDI_FSY NC [1]
E17
FDI_ INT
C17
FDI_LSYN C[0]
F18
FDI_LSYN C[1]
D17
PEG_IC OM PI
B26
PEG _ICO MPO
A26
PE G_ RBIA S
A25
PEG_ R CO MPO
B27
PE G_ RX# [0]
K35
PE G_ RX# [1]
J34
PE G_ RX# [2]
J33
PE G_ RX# [3]
G3 5
PE G_ RX# [4]
G3 2
PE G_ RX# [5]
F34
PE G_ RX# [6]
F31
PE G_ RX# [7]
D3 5
PE G_ RX# [8]
E33
PE G_ RX# [9]
C3 3
PEG_R X# [10 ]
D3 2
PEG_R X# [11 ]
B32
PEG_R X# [12 ]
C3 1
PEG_R X# [13 ]
B28
PEG_R X# [14 ]
B30
PEG_R X# [15 ]
A31
PEG _RX[0]
J35
PEG _RX[1]
H3 4
PEG _RX[2]
H3 3
PEG _RX[3]
F35
PEG _RX[4]
G3 3
PEG _RX[5]
E34
PEG _RX[6]
F32
PEG _RX[7]
D3 4
PEG _RX[8]
F33
PEG _RX[9]
B33
PE G_ RX[10 ]
D3 1
PE G_ RX[11 ]
A32
PE G_ RX[12 ]
C3 0
PE G_ RX[13 ]
A28
PE G_ RX[14 ]
B29
PE G_ RX[15 ]
A30
PEG _TX#[0]
L33
PEG _TX#[1]
M3 5
PEG _TX#[2]
M3 3
PEG _TX#[3]
M3 0
PEG _TX#[4]
L31
PEG _TX#[5]
K32
PEG _TX#[6]
M2 9
PEG _TX#[7]
J31
PEG _TX#[8]
K29
PEG _TX#[9]
H3 0
PE G_ TX#[1 0 ]
H2 9
PE G_ TX#[1 1 ]
F29
PE G_ TX#[1 2 ]
E28
PE G_ TX#[1 3 ]
D2 9
PE G_ TX#[1 4 ]
D2 7
PE G_ TX#[1 5 ]
C2 6
PEG _T X[0]
L34
PEG _T X[1]
M3 4
PEG _T X[2]
M3 2
PEG _T X[3]
L30
PEG _T X[4]
M3 1
PEG _T X[5]
K31
PEG _T X[6]
M2 8
PEG _T X[7]
H3 1
PEG _T X[8]
K28
PEG _T X[9]
G3 0
PEG _TX[10]
G2 9
PEG _TX[11]
F28
PEG _TX[12]
E27
PEG _TX[13]
D2 8
PEG _TX[14]
C2 7
PEG _TX[15]
C2 5
C42 .1U_10V_X7R_04
R475
* 4.7K_04
C28 .1U_10V_X7R_04
C43 .1U_10V_X7R_04
Q3 2
2N 3 90 4
B
E C
C39 .1U_10V_X7R_04
C27 .1U_10V_X7R_04
R4 7 6
*4 .7 K _ 04
C25 .1U_10V_X7R_04
C37 .1U_10V_X7R_04
U36
AD M1032A RM
VD D
1
D+
2
D-
3
TH ERM
4
GND
5
ALE RT
6
SD ATA
7
SC LK
8
C38 .1U_10V_X7R_04
3.3V
VD D3
DM I_ TXP013
DM I_ TXP113
DM I_ TXP213
DM I_ TXN 013
DM I_ TXN 113
DM I_ TXN 213
DM I_ TXP313
DMI_RXN213
DMI_RXN013
DMI_RXN113
DM I_ TXN 313
DMI_RXN313
DMI_RXP013
DMI_RXP113
DMI_RXP213
DMI_RXP313
THE RM _AL ER T# 2 5
R190 10K_04
R1 9 1 * 0_0 4
R477 *20mil_short
VDD 3
3.3V
R4 8 8
*10K_04
RT3
*100K_N TC _06_B
12
R492
*1 0 K_1 % _ 0 4
VDD 3
It applies to Auburndale and Clarksfield discrete graphic designs.
If discrete graphic chip is used for Auburndale, VAXG (GFX core) rail can be connected
to GND if motherboard only support s discrete graphics and also in a common
motherboard design if GFX VR is not stuffed. On the other hand, if the VR is stuffed,
VAXG can be left floating in a common motherboard design (Gfx VR keeps VAXG from
floating).
In addit
ion, FDI_RXN_[7:0] and FDI_RXP_[7:0] can be left floating on the PCH.
FDI_TX[7:0] and FDI_TX#[7:0] can be left floating on the Auburndale.
The GFX_IMON, FDI_FSYNC[0], FDI_FSYNC[1], FDI_LSYNC[0], FDI_LSYNC[1], and
FDI_INT signals should be tied to GND (through 1K ? % resistors) in the common
motherboard design case. Please not that if these signals are left floating, there are no
functional impacts but a small amo
unt of power (~15 mW) maybe wasted. VAXG_SENSE
and VSSAXG_SENSE on Auburndale can be left as no connect.
DPLL_REF_SSCLK and DPLL_REF_SSCLK# can be connected to GND on Auburndale
directly if motherboard only supports discrete graph ics. In a common motherboard
design, these pins are driven via PCH (even if Graph ics is disabled by BIOS) thus no
external termination is required.
RN20
33 _ 4 P 2R _ 04
1 4
2 3
Thermal Sensor
NEAR EC
20 mil
PROCESSOR 1/7 ( DMI,PEG,FDI )
SMC _C PU_THE RM 12 ,25
SMD _C PU_THE RM 12 ,25
PEG_ TX_ 15
PEG_ TX# _1 0
PEG_ TX# _1 3
PEG_ TX_ 13
PEG_ TX_ 2
PEG_ TX# _3
PEG_ TX_ 12
PEG_ TX_ 1
PEG_ TX# _5
PEG_ TX_ 14
PEG_ TX# _2
PEG_ TX# _7
PEG_ TX_ 4
PEG_ TX# _1 4
PEG_ TX# _1 2
PEG_ TX_ 9
PEG_ TX# _6
PEG_ TX_ 8
PEG_ TX_ 6
PEG_ TX# _1
PEG_ TX# _4
PEG_ TX# _9
PEG_ TX# _1 1
PEG_ TX# _1 5
PEG_ TX_ 10
PEG_ TX# _8
PEG_ TX_ 11
PEG_ TX_ 0
PEG_ TX# _0
PEG_ TX_ 7
PEG_ TX_ 3
PEG_ TX_ 5
D03 BOM DEL
R140 1K_04
Sheet 2 of 57
Processor 1/7