Service manual
Schematic Diagrams
Power Block Diagram B - 55
B.Schematic Diagrams
Power Block Diagram
Sheet 54 of 55
Power Block
Diagram
16
AC
ADA PTER
IB EX PE AK
BUF_PLT_RST#
3.3V
SM_DRAMPWROK
RSMRST#
1.8VS
5
1
11
17
DD R1. 5 V _ PW RGD
CPU
ITE 85 12
SLP_S4
SWITCHES
CPU CORE VR
SYSTEM VR
RSTIN#
1.1VS_VTT VR
CLK EN#
1.5V
2
3
7
Startup
Circuit
DD_ON
VCORE_ON
BATTERY
PACK
1.5V
DD _O N
VCORE
1.1VS_VTT_PWRGD
SLG8SP585
DR A MPW RO K
PWR _BTN #
10
SYSTEM VR
SLP_S 4 # (S US C# )
15
12
1.5VS
1.5VS_PWRGD
1.5VS VR
CLK _ PW RG D
DEL A Y _ PW R GD
Button
SB _ PW ROK
SLP_S 3 # (S US B#)
VD D 3
SUSB SUSB#
VIN
VDD 3
VIN
1.1VS_VTT
SLP_S3
SW ITCHE S
VT T_ ME M
1.8VS
3.3VS
VDD 5
VIN
1.5VS_C PU
5VS
1.5V
1.5VS1.8VS
6
SY S _PW ROK
VDD3
VCORE_ON
SUSC#
VI N
5V
PW R_SW #
1.1VS
NC
VD D 5
4
13
DD _ O N#
VCCPWRGOOD_1
1.8VS VR
ALL_SYS_PWRGD
VTT_MEM
PM_PW ROK
PROCPW RGD
VDDPWRGOOD
8
DD _ O N
PLT_RS T#
DDR VR
99ms DELAY
1.8VS_PWRGD
H_CPUPWRGD
14
VCCPWRGOOD_0
9