Service manual

Schematic Diagrams
B - 54 V1.0 Power_SEQ S4
B.Schematic Diagrams
V1.0 Power_SEQ S4
Sheet 53 of 55
V1.0 Power_SEQ
S4
SUSB#
Vcore_ ON
1.49ms
S4 Sleep SEQ
880us(Th)
S4 Wakeup SEQ
Vcore
MEPWROK
379ms
3.3VS
30us(Te)
SYS_PW ROK
1.1VS
30us(Td)
30us(Ti)
2.588ms
DRAMPW ROK
SUSC#
4.02ms(Tj)
limit to 0 ms(Tk)
V
CCPWRG OOD
SUS_ST ATE#
48us(Tn)
PLTRST#
384us(Tm)
>40ns,PASS
310us(Tc)
6.4ms
Bios: 1.00.E1
EC: 1.00.E1b-TEST
Test date: 2009/7/21
760us
1.596ms
1.736ms
>40ns,PASS
>40ns,PASS
>5us,PASS
>0ms,PASS
<100ns,FAIL
>30us,PASS
>-100ns,PASS
>210us,PASS
X8100 V1.0 POWER SEQUENCE S4 AND WAKE-UP