Service manual

Schematic Diagrams
Yonah 1/2 B - 3
B.Schematic Diagrams
Yonah 1/2
Sheet 2 of 34
Yonah 1/2
R327
27.4_1%_04
R39
4.7K_04
AC
D11 SCS751V
C206
0.01u_04
H_IERR#
C229
1u/6.3V_X7R
R84 150_1%_04
+V_THRM
+H8VCC
+H8VCC
+1.05VS
+1. 05VS
H_ADSTB#04
H_REQ#[4:0]4
+3VS
H_A#[31:3]4
H_A#[31:3]4
H_ADSTB#14
Zo=60 Ohm
Zo=60 Ohm
H_DINV#04
H_D#[63:0]4
H_DSTBN#04
H_D#[63:0]4
Z0206
H_DSTBP#14
H_DSTBN#14
H_DSTBP#04
Z0208
Z0205
CPU_BSEL04
PM_THRMTRIP# 5,14
H_DINV#14
PM_THRMTRIP# 5,14
CPU_BSEL24
CPU_BSEL14
Z0207
H_A20M#14
H_STPCLK#14
H_IGNNE#14
H_SMI#14
H_BPRI# 4
H_TRDY# 4
H_INTR14
H_NMI14
H_RS#2 4
H_INIT# 14
H_DEFER# 4
H_RS#1 4
H_CPURST# 4
H_RS#0 4
H_CPUSLP# 4
H_DPWR# 4
H_DPRSTP# 14,29
H_DPSLP# 14
TH ERM_TRI P# 23
H_FERR#14
TH ERMAL_RST#23
H_PWRGD 14
H_LOCK# 4
H_HIT# 4
PM_THRM# 16
H_DBSY# 4
H_HITM# 4
H_DRDY# 4
H_BR0# 4
H_DSTBP#2 4
H_ADS# 4
H_BNR# 4
H_DSTBN#2 4
H_D#[63:0] 4
H_D#[63:0] 4
H_DSTBN#3 4
H_DINV#3 4
H_DINV#2 4
CLK_CPU_BCLK 19
SMD_THERM 23
SMC_THERM 23
H_DSTBP#3 4
+3VS 5,8,9,10,13,14,15,16,17,18,19,20,21,22,24,25,26,27
+1.05VS 3,4,7,8,9,14,17,31
PSI# 29
CLK_CPU_BCLK# 19
Z0210
+H8VCC 19,23,27,30,32
Z0211
Z0209 Z0217
Z0216
Z0219
Z0218
Z0220
COMP0
COMP3
COMP2
Z0215
COMP1
H_TMS
H_TDI
Z0213
Z0214
Z0212
H_A#9
H_A#4
H_REQ#4
H_A#3
H_A#7
H_REQ#2
H_A#6
H_A#8
H_REQ#3
H_REQ#0
H_REQ#1
H_A#5
H_A#10
H_A#12
H_A#15
H_A#22
H_A#14
H_A#17
H_A#23
H_A#25
H_A#21
H_A#16
H_A#24
H_A#11
H_A#18
H_A#20
H_A#19
H_A#13
H_A#26
H_A#30
H_A#27
H_A#31
H_A#28
H_A#29
H_D#3
H_D#4
H_D#12
H_D#0
H_D#8
H_D#6
H_D#10
H_D#7
H_D#2
H_D#11
H_D#13
H_D#9
H_D#1
H_D#23
H_D#16
H_D#21
H_D#18
H_D#19
H_D#20
H_D#24
H_D#15
H_D#17
H_D#22
H_D#26
H_D#14
H_D#25
H_D#31
H_D#27
H_D#30
H_D#28
H_D#29
H_D#5
H_TRST#
H_TCK
translation
+1.05VS
H_PROCHOT#
R82 56_04
CPU_GTLREF
ITP_DBRST#
Layout Note:
Z0221
Z0222
H_D#32
H_D#33
H_THERMDA
H_THERMDC
H_D#34
TZ 0202
H_D#35
package: 0402
H_D#36
H_D#37
H_D#38
H_D#39
R583 *0_04
H_D#40
H_D#41
If PROCHOT# is not used, then it must be
terminated with a 56 ¡Ó5% pull-up resistor
to VCCP.The R_isolate can be placed
anywhere as long as it does not have a
stub.L1, L2 and L5 can be routed on
different layers.
If PROCHOT# is routed between CPU and IMVP6
VR , Rtt has to be 68 ¡Ó5%.
If PROCHOT# is routed between CPU, IMVP6 VR
and GMCH, Rtt has to be 75 ¡Ó5%.
R584 *0_04
13-51R11-28C
H_D#42
R585 0_04
Z0227
H_D#43
H_IERR#
H_D#44
C444 0.01u_04
9/13 4.0
H_D#45
9/13 4.0
9/13 4.0
9/13 4.0
R296
100K_04
H_D#46
Z0225
H_D#47
Layout Note:
Route H_THERMDA and
H_THERMDC on same layer.
10 mil trace on 10 mil spacing.
Near to Thermal
IC
H_D#48
0.5" max, Zo= 55 Ohms
Within 2.0" of the CPU
Z0226
H_D#49
H_D#50
H_D#51H_BPM0#
H_D#52H_BPM1#
H_D#53H_BPM2#
H_D#54H_BPM3#
Layout Note:
Z0201
H_D#55
Z0202
H_PRDY#
H_D#56
Z0203
Z0204
H_PREQ#
H_D#57
Layout note:
Layout Note:
H_PREQ#
H_TCK
H_D#58
FROM IMVP6
H_TDI
Z0224
H_D#59
Z0223
H_TDO
H_D#60H_TMS
H_D#61
Zo=55 Ohm
Zo=55 Ohm
H_TRST#
H_D#62ITP_DBRST#
H_D#63
H_PROCHOT#
H_THERMDA
H_THERMDC
COMP0
COMP0, COMP2: 0.5" Max, Zo=27.4 Ohms
COMP1, COMP3: 0.5" Max, Zo=55 Ohms
Best estimate is 18 mils wide trace for outer
layers and 14 mils wide trace if on internal
layers.
Layout note:
PM_THRMTRIP# should connect to
ICH7 and GMCH without T-ing
COMP1
COMP2
COMP3
Voltage
R38
10K_04
A[3]#
J4
A[4]#
L4
A[5]#
M3
A[6]#
K5
A[7]#
M1
A[8]#
N2
A[9]#
J1
A[10]#
N3
A[11]#
P5
A[12]#
P2
A[13]#
L1
A[14]#
P4
A[15]#
P1
A[16]#
R1
ADSTB[0]#
L2
REQ[0]#
K3
REQ[1]#
H2
REQ[2]#
K2
REQ[3]#
J3
REQ[4]#
L5
A[17]#
Y2
A[18]#
U5
A[19]#
R3
A[20]#
W6
A[21]#
U4
A[22]#
Y5
A[23]#
U2
A[24]#
R4
A[25]#
T5
A[26]#
T3
A[27]#
W3
A[28]#
W5
A[29]#
Y4
A[30]#
W2
A[31]#
Y1
ADSTB[1]#
V4
A20M#
A6
FERR#
A5
IGNNE#
C4
STPCLK#
D5
LINT0
C6
LINT1
B4
SMI#
A3
RSVD[01]#
AA1
RSVD[02]#
AA4
RSVD[03]#
AB2
RSVD[04]#
AA3
RSVD[05]#
M4
RSVD[06]#
N5
RSVD[07]#
T2
RSVD[08]#
V3
RSVD[09]#
B2
RSVD[10]#
C3
RSVD[11]#
B25
RSVD[12]#
T22
RSVD[13]#
D2
RSVD[14]#
F6
RSVD[15]#
D3
RSVD[16]#
C1
RSVD[17]#
AF1
RSVD[18]#
D22
RSVD[19]#
C23
RSVD[20]#
C24
BCLK[0]
A22
BCLK[1]
A21
PROCHOT
D21
TH ERMD A
A24
THERMDC
A25
THER MTRI P#
C7
BPM[0]#
AD4
BPM[1]#
AD3
BPM[2]#
AD1
BPM[3]#
AC4
PRDY #
AC2
PREQ#
AC1
TCK
AC5
TD I
AA6
TD O
AB3
TMS
AB5
TR ST#
AB6
DBR#
C20
HIT#
G6
HITM#
E4
RESET#
B1
RS[0]#
F3
RS[1]#
F4
RS[2]#
G3
TR DY #
G2
IERR#
D20
INIT#
B3
LOCK#
H4
BR0#
F1
DEFER#
H5
DRDY#
F21
DBSY#
E1
ADS#
H1
BNR #
E2
BPRI#
G5
NC
A2
RESERVED
ADDR GROUP 0
CONTROL
XDP/ITP SIGNALS
THERMH CLK
U28A
CPU
R331
54.9_1%_04
D[0]#
E22
D[1]#
F24
D[2]#
E26
D[3]#
H22
D[4]#
F23
D[5]#
G25
D[6]#
E25
D[7]#
E23
D[8]#
K24
D[9]#
G24
D[10
J24
D[11]#
J23
D[12]#
H26
D[13]#
F26
D[14]#
K22
D[15]#
H25
DSTBN[0]#
H23
DSTBP[0]#
G22
DINV[0]#
J26
D[16]#
N22
D[17]#
K25
D[18]#
P26
D[19]#
R23
D[20]#
L25
D[21]#
L22
D[22]#
L23
D[23]#
M2 3
D[24]#
P25
D[25]#
P22
D[26]#
P23
D[27]#
T24
D[28]#
R24
D[29]#
L26
D[30]#
T25
D[31]#
N24
DSTBN[1]#
M2 4
DSTBP[1]#
N25
DINV[1]#
M2 6
GTLREF
AD26
TEST 1
C26
TEST 2
D25
BSEL[0]
B22
BSEL[1]
B23
BSEL[2]
C21
COMP[0]
R26
COMP[1]
U26
COMP[2]
U1
COMP[3]
V1
DPRSTP#
E5
DPSLP#
B5
DPWR#
D24
PWR GOOD
D6
SLP#
D7
PSI#
AE6
D[48]#
AC22
D[49]#
AC23
D[50]#
AB22
D[51]#
AA21
D[52]#
AB21
D[53]#
AC25
D[54]#
AD20
D[55]#
AE22
D[56]#
AF23
D[57]#
AD24
D[58]#
AE21
D[59]#
AD21
D[60]#
AE25
D[61]#
AF25
D[62]#
AF22
D[63]#
AF26
DSTBN[3]#
AD23
DSTBP[3]#
AE24
DINV[3]#
AC20
D[32]#
AA23
D[33]#
AB24
D[34]#
V24
D[35]#
V26
D[36]#
W25
D[37]#
U23
D[38]#
U25
D[39]#
U22
D[40]#
AB25
D[41]#
W22
D[42]#
Y23
D[43]#
AA26
D[44]#
Y26
D[45]#
Y22
D[46]#
AC26
D[47]#
AA24
DSTBN[2]#
W24
DSTBP[2]#
Y25
DINV[2]#
V23
DATA GRP 3
DATA GRP 0 DATA GRP 1
MISC
DATA GRP 2
U28B
CPU
R335 39_1%_04
R297 330K_04
R174
2K_1%_04
R337 680_04
R306 51. 1_1%_04
R83 56_04
R333 150_1%_04
C212
0.1u_X7R_04
C428
1000p_04
R304 *1K_04
G
DS
Q51
NDS352
R325
27.4_1%_04
VDD
1
D+
2
D-
3
TH ER M
4
GND
5
ALERT
6
SDATA
7
SCLK
8
U26
ADM1032
R338 27_04
R339 54.9_1%_04
R286 0_04
G
DS
Q52
2N7002W
C422
*1u/10V
R170 1K_1%_04
R284
100K_04
R326
54.9_1%_04
R40
4.7K_04