Service manual

Schematic Diagrams
Clock Generator B - 21
B.Schematic Diagrams
Clock Generator
Sheet 20 of 57
Clock Generator
CLK_SCLK
CLK_SCLK
CLK_SDATA
CLK_PWRGD
CLK_SDATA
XO U T
REF_0/CPU_SEL
REF_0/CPU_SEL
3.3VS3,9,10,11,12,13,15,16,17,18,21,22,23,24, 25,26,27,28,29,30,31,32,33,34,39
CLK_CPU1#
CLK_CPU1
XI N
R34 2.2K_04
C100
0.1u_10V_X7R_04
C83
33p_50V_NPO_04
C60
0.1u_10V_X7R_04
RN3
0_4P2R_04
1 4
2 3
C61 *10p_50V_04
Q3
MTN7002ZHS3
G
D S
C59
0.1u_10V_X7R_04
C76
10u_6.3V_X5R_06
R33 2.2K_04 X1 X8A01431AFK1H_14.31818MHz
12
R29 *4.7K_04
C86
10u_6.3V_X5R_06
RN4
0_4P2R_04
1 4
2 3
R28 10K_04
.
L11 HCB1608KF-121T25
C92
0.1u_10V_X7R_04
C99
0.1u_10V_X7R_04
C101
0.1u_10V_X7R_04
C90
33p_50V_NPO_04
C58
0.1u_10V_X7R_04
R58 2.2K_04
U7
SLG8SP585
VDD_DOT
1
VDD_27
5
VDD_SRC
17
VDD_CPU
24
VDD_REF
29
VSS_DOT
2
XTA L_OU T
27
XTA L_I N
28
REF_0/CPU_SEL
30
SDA
31
SCL
32
VSS_27
8
VSS_SATA
9
VSS_SRC
12
VSS_CPU
21
VSS_REF
26
VDD_SRC_I/O
15
VDD_CPU_I/O
18
DOT_96
3
DOT_96#
4
27M
6
27M_SS
7
SRC_1/SATA
10
SRC_1#/SATA#
11
SRC_2
13
SRC_2#
14
CPU_STOP#
16
CPU_1
20
CPU_1#
19
CPU_0
23
CPU_0#
22
CKPWRGD/PD#
25
VSS
33
Q4
MTN7002ZHS3
G
D S
R59 *0_04
RN1
0_4P2R_04
1 4
2 3
RN2
0_4P2R_04
1 4
2 3
R41 33_04
.
L10 HCB1608KF-121T25
CLK_VCC2CLK_VCC1
3.3VS
CLK_VCC1
CLK_VCC2
3.3VS
1.1VS
3.3VS5VS
CLK_VCC1
1.1VS
CLK_BUF_REF1412
CLK_BUF_DOT96_N 12
CLK_BUF_DOT96_P 12
CLK_PCIE_ICH# 12
CLK_SATA 12
CLK_PCIE_ICH 12
CLK_SATA# 12
CLK_BUF_BCLK_N 12
CLK_BUF_BCLK_P 12
SMB_DATA9,10,12
SMB_CLK9,10,12
CPU_STOP#
REF_0/CPU_SEL
C87
*.1U_10V_X7R_04
R56
10K_04
Q10
MTN 7002ZHS3
G
DS
R53
1M_04
CLKEN#39
3.3VS
XO UT
XI N
SMBus
EMI
EMI Capactior
1(0.7V-1.5V)
VDD_I/O can be
ranging from
1.05V to 3.3V
0(default)
PIN_30
0.1uF near the every power pin
CLOCK GENERATOR
100MHz
CPU_1
0.1uF near the every power pin
100MHz
CPU_0
133MHz133MHz
CLKGEN POWER
CPU_SEL_During CK_PEWGD Latch Pinl
5VS18,22,23,24,25,28,30,31,32,33,34,39
1.1VS6,11,12,13,17,18,36,38,39