Service manual

Schematic Diagrams
B - 4 NPT 64 (P2) DDR2_A
B.Schematic Diagrams
NPT 64 (P2) DDR2_A
MEM_A_CS2#
MEM_A_CS3#
MEM_A_ADD[0..15]
MEM_A_CS0#
MEM_A_CS1#
MEM_A_CKE0
MEM_A_CKE1
MEM_A_BANK0
MEM_A_ODT0
MEM_A_ODT1
MEM_A_WE#
MA_DATA[45]
AD21
MA_ADD[1]
N21
MA_ADD[2]
N22
MA_ADD[3]
M2 2
MA_ADD[4]
M2 4
MA_ADD[5]
M2 0
MA_ADD[6]
M1 9
MA_ADD[7]
L21
MA_ADD[8]
L22
MA_ADD[9]
L19
MA_ADD[10]
R19
MA_ADD[11]
L20
MA_ADD[12]
K24
MA_ADD[13]
V24
MA_ADD[14]
K20
MA_ADD[15]
K19
MA_DATA[0]
G12
MA_DATA[1]
F12
MA_DATA[2]
H14
MA_DATA[3]
G14
MA_DATA[4]
H11
MA_DATA[5]
H12
MA_DATA[6]
C13
MA_DATA[7]
E13
MA_DATA[8]
H15
MA_DATA[9]
E15
MA_DATA[10]
E17
MA_DATA[11]
H17
MA_DATA[12]
E14
MA_DATA[13]
F14
MA_DATA[14]
C17
MA_DATA[15]
G17
MA_DATA[16]
G18
MA_DATA[17]
C19
MA_DATA[18]
D22
MA_DATA[19]
E20
MA_DATA[20]
E18
MA_DATA[21]
F18
MA_DATA[22]
B22
MA_DATA[23]
C23
MA_DATA[24]
F20
MA_DATA[25]
F22
MA_DATA[26]
H24
MA_DATA[27]
J19
MA_DATA[28]
E21
MA_DATA[29]
E22
MA_DATA[30]
H20
MA_DATA[31]
H22
MA_DATA[32]
Y24
MA_DATA[33]
AB24
MA_DATA[34]
AB22
MA_DATA[35]
AA21
MA_DATA[36]
W22
MA_DATA[37]
W21
MA_DATA[38]
Y22
MA_DATA[39]
AA22
MA_DATA[40]
Y20
MA_DATA[41]
AA20
MA_DATA[42]
AA18
MA_DATA[43]
AB18
MA_DATA[44]
AB21
MA_ADD[0]
R21
MA_DATA[46]
AD19
MA_DATA[47]
Y18
MA_DATA[48]
AD17
MA_DATA[49]
W16
MA_DATA[50]
W14
MA_DATA[51]
Y14
MA_DATA[52]
Y17
MA_DATA[53]
AB17
MA_DATA[54]
AB15
MA_DATA[55]
AD15
MA_DATA[56]
AB13
MA_DATA[57]
AD13
MA_DATA[58]
Y12
MA_DATA[59]
W11
MA_DATA[60]
AB14
MA_DATA[61]
AA14
MA_DATA[62]
AB12
MA_DATA[63]
AA12
MA0_ODT[0]
U19
MA0_ODT[1]
V20
MA _C K E[ 0 ]
J21
MA _C K E[ 1 ]
J20
MA 0_C S* [ 0 ]
T19
MA 0_C S* [ 1 ]
V22
MA 0_C S* [ 2 ]
J22
MA 0_C S* [ 3 ]
V19
MA_W E*
U21
MA_CAS*
U20
MA_RAS*
T20
MA_BANK[0]
T22
MA_BANK[1]
R20
MA_BANK[2]
K22
MA0_CLK*[ 2]
AA16
MA0_C LK[ 2]
Y16
MA0_CLK*[ 1]
F16
MA0_C LK[ 1]
E16
MA_DQS*[0]
H13
MA_DQS*[1]
G15
MA_DQS*[2]
C21
MA_DQS*[3]
G21
MA_DQS*[4]
AC23
MA_DQS*[5]
AB20
MA_DQS*[6]
W15
MA_DQS*[7]
W13
MA_DQS[ 0]
G13
MA_DQS[ 1]
G16
MA_DQS[ 2]
C22
MA_DQS[ 3]
G22
MA_DQS[ 4]
AD23
MA_DQS[ 5]
AB19
MA_DQS[ 6]
Y15
MA_DQS[ 7]
W12
MA_DM[0]
E12
MA_DM[1]
C15
MA_DM[2]
E19
MA_DM[3]
F24
MA_DM[4]
AC24
MA_DM[5]
Y19
MA_DM[6]
AB16
MA_DM[7]
Y13
MEMORY_A
SEC 3 OF 6
?
U53C
PZ638X3-284S-01
C983
1.5P_0402
C982
1.5P_0402
MEM_A_CAS# 7
MEM_A_RAS# 7
MEM_A_CS2# 7
MEM_A_BANK1 7
MEM_A_BANK2 7
MEM_A_BANK0 7
MEM_A_CKE0 7
MEM_A_CS0# 7
MEM_A_CS1# 7
MEM_A_CS3# 7
MEM_A_DATA[0..63]7
MEM_A_ODT0 7
MEM_A_ODT1 7
MEM_A_CKE1 7
MEM_A_WE# 7
MEM_A_CLK1 # 7
MEM_A_CLK2 # 7
MEM_A_CLK2 7
MEM_A_CLK1 7
MEM_A_DQS#[ 7. .0]
ME M_A _DA TA0
MEM_A_DQS[7. .0]
MEM_A_DQM[ 7.. 0]
ME M_A _DA TA1
ME M_A _DA TA2
ME M_A _DA TA3
ME M_A _DA TA4
ME M_A _DA TA5
ME M_A _DA TA6
ME M_A _DA TA7
ME M_A _DA TA8
ME M_A _DA TA1 1
ME M_A _DA TA1 2
ME M_A _DA TA1 0
ME M_A _DA TA9
ME M_A _DA TA1 4
ME M_A _DA TA1 5
ME M_A _DA TA1 3
ME M_A _DA TA2 0
ME M_A _DA TA1 8
ME M_A _DA TA1 7
ME M_A _DA TA2 2
ME M_A _DA TA2 3
ME M_A _DA TA2 1
ME M_A _DA TA1 6
ME M_A _DA TA1 9
ME M_A _DA TA2 5
ME M_A _DA TA3 0
ME M_A _DA TA3 1
ME M_A _DA TA2 9
ME M_A _DA TA2 4
ME M_A _DA TA2 7
ME M_A _DA TA2 8
ME M_A _DA TA2 6
ME M_A _DA TA3 9
ME M_A _DA TA3 7
ME M_A _DA TA3 2
ME M_A _DA TA3 5
ME M_A _DA TA3 6
ME M_A _DA TA3 4
ME M_A _DA TA3 3
ME M_A _DA TA3 8
MEM_A_DATA[0..63]
ME M_A _DA TA4 0
ME M_A _DA TA4 3
ME M_A _DA TA4 4
ME M_A _DA TA4 2
ME M_A _DA TA4 1
ME M_A _DA TA4 6
ME M_A _DA TA4 7
ME M_A _DA TA4 5
ME M_A _DA TA5 2
ME M_A _DA TA5 0
ME M_A _DA TA4 9
ME M_A _DA TA5 4
ME M_A _DA TA5 5
ME M_A _DA TA5 3
ME M_A _DA TA4 8
ME M_A _DA TA5 1
ME M_A _DA TA5 7
ME M_A _DA TA6 2
ME M_A _DA TA6 3
ME M_A _DA TA6 1
ME M_A _DA TA5 6
ME M_A _DA TA5 9
ME M_A _DA TA6 0
ME M_A _DA TA5 8
MAX NECKDOWN TO & FROM CAPS IS 500MILS
TRACE FROM CAP TO CPU MUST BE LESS THAN 1200MILS
MEM_A_ADD[0..15]7
MEM_A_DQM[ 7. .0] 7
MEM_A_DQS[ 7. .0] 7
MEM_A_DQS#[ 7. .0] 7
ME M_A _AD D0
MEM_ A_D QM7
ME M_A _AD D1
MEM_ A_D QM6
ME M_A _AD D2
MEM_ A_D QM5
ME M_A _AD D3
MEM_ A_D QM4
MEM_ A_D QM3
ME M_A _AD D7
ME M_A _AD D5
ME M_A _AD D6
ME M_A _AD D4
MEM_ A_D QM2
ME M_A _AD D1 1
ME M_A _AD D9
ME M_A _AD D1 0
ME M_A _AD D8
MEM_ A_D QM1
ME M_A _AD D1 5
ME M_A _AD D1 3
ME M_A _AD D1 4
ME M_A _AD D1 2
MEM_ A_D QM0
MEM_A_CLK1
MEM_A_CLK2#
MEM_A_CLK2
MEM_A_DQS4
MEM_A_DQS3
MEM_A_DQS2
MEM_A_DQS7
MEM_A_DQS0
MEM_A_DQS6
MEM_A_DQS5
MEM_A_DQS1
MEM_A_CLK1#
MEM_A_DQS#2
MEM_A_DQS#7
MEM_A_DQS#0
MEM_A_DQS#6
MEM_A_DQS#5
MEM_A_DQS#1
MEM_A_DQS#4
MEM_A_DQS#3
MEM_A_BANK1
MEM_A_BANK2
MEM_A_CAS#
MEM_A_RAS#
Sheet 3 of 46
NPT 64 (P2)
DDR2_A