Service manual

Table Of Contents
Schematic Diagrams
Mainboard (71-P3000-004A) B - 7
Schematic Diagrams
CPU (P4 mPGA478) - 2 of 2
Sheet 5 of 32
CPU (P4 mPGA478)
2 of 2
VCORE
VCORE
VCORE
VCORE
VCORE
FERR#
BR0#
PROCHOT#
CPUPWRGD
THERMTRIP#
TDI
TMS
HCPURST#
TDO
DBR#
TCK
TRS T#
Z0403
Z0404
IERR#
Z0415
Z0408
Z0407
Z0412
TDI
Z0410
FERR#
Z0416Z0406
COMP1
TCK
HCPURST#
Z0401
Z0409
COMP0
BR0#
PROCHOT#
TDO
CPUPWRGD
Z0413
Z0405
TMS
IERR#
TRS T#
THERMTRIP#
Z0414
DBR#
GTLREF0
Z0402
GTLREF1
T293
T294
C192
1U/6.3V_X7R
12
C180
1U/6.3V_X7R
12
C161
220P
12
C162
220P
12
R111
100_1%
12
R112
100_1%
12
R452 62_1%12
R423 51_1%12
R444 62_1%12
R88 300_1%12
R135 62_1%12
R438 150_1%12
R435 3912
R99 51_1%12
R134 7512
R89 150_1%12
R449 2712
R451 68012
R410 51_1%12
T295
R74 1_08051 2
+
CP2 33U/10V_C
1 2
L14 4.7UH_08051 2
T291
R73 1_08051 2
T296
R113 49.9_1%1 2
T292
L15 4.7UH_08051 2
R406 51_1%12
+
CP1 33U/10V_C1 2
R133 *R12
R114 49.9_1%1 2
T290
T297
R388 62_1%12
U11B
NORTHWOOD478
AC1
V5
A5
AC26
AD26
AE25
L5
R5
P1
E5
D1
F6
F20
AA6
AA21
W23
P23
J23
F21
W22
R22
K22
E22
AF23
AF22
AC3
V6
B6
Y4
AA3
W5
AB2
H5
H2
J6
G1
G4
H6
G2
F3
E3
D2
E2
D4
C1
F7
E6
D5
B3
C4
A2
C3
B2
B5
C6
AB26
AB23
AB25
A4
V21
P26
G25
E21
C25
C5
C7
C9
D10
D12
D14
D16
D18
D20
D21
D24
D3
D6
D8
AE23
AD20
AD22
K24
K3
K6
L1
L23
L26
L4
M2
M22
M25
M5
N21
N24
N3
N6
P2
P22
P25
P5
E13
E15
E17
E19
E23
E26
E4
E7
E9
F10
F12
F14
F16
F18
F2
F22
F25
F5
J2
J22
J25
J5
K21
R1
R23
T6
U2
U22
U25
U5
V1
V23
V26
V4
W21
W24
W3
W6
Y2
Y22
Y25
Y5
G6
R26
E11
E1
F8
G21
G24
T3
T24
T21
G3 R4
AF3
AD6
AD5
L24
AF4
C22
AP0
AP1
VCC_SENSE
ITP_CLK0
ITP_CLK1
DBRESET
ADSTB0
ADSTB1
COMP1
LINT1
LINT0
GTLREF3
GTLREF2
GTLREF1
GTLREF0
STBP3
STBP2
STBP1
STBP0
STBN3
STBN2
STBN1
STBN0
BCLK1
BCLK0
IERR
MCERR
FERR
STPCLK
BINIT
INIT
RSP
DBSY
DRDY
TRDY
ADS
LOCK
BR0
BNR
HIT
HITM
BPRI
DEFER
TCK
TDI
TMS
TRS T
TDO
THE RMDA
THE RMDC
THE RMTRIP
PROCHOT
IGNNE
SMI
A20M
SLP
PWRGOOD
RESET
VSS_SENSE
DB#3
DB#2
DB#1
DB#0
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VCCIOPLL
VCCA
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS VSS
VCCVIDPRG
BSEL0
BSEL1
COMP0
VCCVID
VSS
C181
220P
12
C191
220P
12
SMI# [15]
HIT# [5]
IGNNE# [15]
BR0# [5]
DBSY# [5]
HLOCK# [5]
FERR# [15]
HDRDY# [5]
DEFER# [5]
HITM# [5]
CPUSLP# [15]
INIT# [15]
A20M# [15]
BPRI# [5]
HSTPCLK# [15]
THERMDA [22]
HCPURST# [5]
ADS# [5]
HTRDY# [5]
CPUPWRGD
VCORE [15,26]
THERMDN [22]
CPUCLK#[1]
ITPCLK[1]
HDSTBP0#[5]
NMI[15]
INTR[15]
HDSTBN0#[5]
CPUCLK[1]
HDBI3#[5]
HDSTBN1#[5]
HDSTBP2#[5]
ITPCLK#[1]
HADSTB0#[5]
HADSTB1#[5]
HDSTBP3#[5]
HDSTBP1#[5]
HDSTBN3#[5]
HDSTBN2#[5]
BNR# [5]
HDBI2#[5]
HDBI1#[5]
HDBI0#[5]
VCCVID
GTLREF GENERATION CIRCUITS
CPU SIGNAL TERMINATION
CLOSE TO CPU
LAYOUT NOTICE:
GTLREF0, GTLREF1 1.5inches max.
LAYOUT NOTICE:
THERMDA,THERMDN:
10 mils width and spacing of 10 mils is recommand.
Parallel connect to U18(W83627HF)
VCCVID=
1.2V 40mA
AF3 is reserved pin
VCORE
C181/
C180
R114/
R113
AA6/
AA21
F6/
F20
C192/
C191
C162/
C161
R112/
R111
1.5" Max 1.5" Max
GTLREF1/
GTLREF0