Service manual
Table Of Contents
- Manual
- Preface
- 1: Introduction
- 2: Disassembly
- Overview
- Disassembly Steps
- To remove the hard disk drive assembly:
- To remove the CD device(s):
- To remove the RF module:
- To remove the system memory:
- To remove the CPU:
- To remove the modem:
- To remove the floppy disk drive assembly:
- To remove the optional wireless LAN module:
- To remove the inverter board:
- To remove the mainboard:
- To remove the LCD/LED board:
- To remove the base cover:
- To remove the speaker units:
- To remove the bridge board:
- To remove the CD device base brackets:
- To remove the USB board:
- To remove the power supply unit:
- Removing the Hard Disk Drive Assembly
- Removing the CD Devices
- Removing the RF Module
- Removing the System Memory
- Removing the CPU
- Removing the Modem
- Removing the Floppy Disk Drive Assembly
- Removing the Wireless LAN Module
- Removing the I/O Bracket
- Removing the Rear Bracket
- Removing the Inverter Board
- Removing the Mainboard
- Separating the Bottom Case from the LCD & Mainboard Assembly
- Removing the LCD
- Removing the LED Board
- Removing the Base Cover
- Removing the Speaker Units
- Removing the Bridge Board
- Removing the CD Device Base Brackets
- Removing the USB Board
- Removing the Power Supply Unit
- Appendix A: Part Lists
- Appendix B: Schematic Diagrams
- Table 1 - 1 Schematic Diagram
- System Block Diagram
- Clock Generator
- DRCG Panel Type
- CPU (P4 mPGA 478) - 1 of 2
- CPU (P4 mPGA478) - 2 of 2
- MCH (CPU, HUB, AGP) - 1 of 2
- MCH (RDRAM, PCI) - 2 of 2
- RAMBUS A,B
- CPU Decoupling
- ATI Mobility M6 - 1 of 3
- ATI Mobility M6 - 2 0f 3
- ATI Mobility M6 - 3 0f 3
- VRAM Terminator
- Z3, LVDS
- Micro-P, LCD PWR
- ICH2 - 1 of 2
- ICH2 - 2 of 2
- Audio Codec, AMP
- IDE, PCI Reset
- PCMCIA 1394
- 1394 PHY, PCMCIA Ejecter
- LAN 8139C
- Super I/O
- USB, Bluetooth
- LPT, IR/RF
- Mini PCI, MDC
- Power - 1 of 2
- Power - 2 of 2
- SSC, VGA Power
- VRAM DDR - 1 of 2
- VRAM DDR - 2 of 2
- Video In
- External USB Board
- LED Board
- Inverter Board - Page 1 of 2
- Inverter Board - Page 2 of 2
- Appendix C: Switches
- Appendix D: Updating the FLASH ROM BIOS
Schematic Diagrams
B - 4 Mainboard (71-P3000-004A)
Schematic Diagrams
Clock Generator
Sheet 2 of 32
CLK GEN
+3VCLK
+3V
+3VCLK
+3VCLK
+3VCLK
+3VCLK
+3V
+3V
+3VCLK
PCICLK0
PCICLK1
3VMREF_B
3VMREF
PCICLK2
3V66_3
3V66_2
PCICLK3
PCICLK4
PCICLK5
SEL100/133
MSEL0
FS0
FS1
Z0104
PCICLK6
MSEL1
3V66_1
3V66_0
FS2
FS3
FS1
FS0
CPUCLKC3
CPUCLKC2
CPUCLKT1
CPUCLKT2
CPUCLKC0
CPUCLKT3
CPUCLKT0
CPUCLKC1
Z0101Z0102
Z0103
MSEL1
MSEL0
R696 *10K1 2
R698 *10K1 2
R695 *10K1 2
R697 *10K1 2
T490
R335
51_1%
12
C90
5P
12
R339
51_1%
12
R338
51_1%
12
R334
51_1%
12
R336
51_1%
12
R337
51_1%
12
R312 331 2
R313 331 2
R57
475_1%
12
R67 331 2
R64 331 2
C531
*C
1 2
R314 331 2
R65 331 2
R68 331 2
L10 0_12061 2
C529
*C
1 2
R322 4.7K1 2
R309 4.7K1 2
R320 331 2
R315 331 2
C94
0.1U_X7R
12
R316 331 2
R308 *R1 2
R319 331 2
C89
10U/10V
12
C69
4.7U/10V
12
C499
10P
12
C500
10P
12
C501
10P
12
C502
10P
12
C503
10P
12
C504
10P
12
R321 331 2
R318 331 2
C498 *C1 2
C506
10P
1 2
C507
10P
1 2
R58 331 2
C532
10P
12
C533
10P
12
C530
10P
12
T3
C92
0.1U_X7R
12
C93
0.1U_X7R
12
C97
0.1U_X7R
12
C98
0.1U_X7R
12
C58
0.1U_X7R
12
C64
0.1U_X7R
12
C99
0.1U_X7R
12
C57
0.1U_X7R
12
C60
0.1U_X7R
12
R307 4701 2
C59
0.1U_X7R
12
C62
0.1U_X7R
12
C61
0.1U_X7R
12
C95
0.1U_X7R
12
C96
0.1U_X7R
12
R306 10K1 2
R36 10K1 2
R39 10K1 2
R311 10K1 2
R62 331 2
R63 331 2
T1
R66 331 2
R61 331 2
T2
R60 331 2
R59 331 2
Y1
14.318MHZ
1 2
U7
ICS9250-37
1
7
13
19
24
32
33
37
40
46
53
4
10
16
22
27
29
36
38
43
49
56
8
9
11
12
14
15
17
18
20
21
23
25
26
28
30
31
34
35
39
42
45
48
51
41
44
47
50
52
54
55
5
6 2
3
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
GND10
GND11
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
PCICLK6
PCICLK7/FS2
PCICLK8/FS3
PCICLK9/SEL100/133
SDATA
FS0/48MHZ_0
FS1/48MHZ_1
PD#
3V66_0
3V66_1
3V66_2
3V66_3
IREF
CPUCLKT0
CPUCLKT1
CPUCLKT2
CPUCLKT3
CPUCLKC0
CPUCLKC1
CPUCLKC2
CPUCLKC3
SCLK
3VMREF_B
3VMREF
X1
X2 MULTSEL0/REF0
MULTSEL1REF1
C73
5P
12
R45 0
1 2
R665 10K1 2
R666 10K1 2
CPUCLK [4]
CPUCLK# [4]
ITPCLK [4]
ITPCLK# [4]
MCHCLK [5]
MCHCLK# [5]
CLKREF1[2]
CLKREF2[2]
MCH66IN[5]
ICH48CLK
ICH66CLK
SMBDATA[7,15,22]
SMBCLK[7,15,22]
LANPCLK
CBPCLK [19]
SIOPCLK
FWHCLK [15]
MINIPCICLK
ICH2PCLK
ICH14CLK [15]
SIO48MHZ
ATI66CLK[9]
+3V [3,10,11,13,14,26,27,28,31]
SUSB#[16,23,26]
Iref=2.32mA
0.5" MAX
0-0.2 inches
R to Node:
0.2" MAX
Node to chip:
12" MAX
LOW FOR 100MHZ OPERATION
CLOCK NOTICE:
Spacing to other traces: 25mils
Line width: 7.0mils
0.5" MAX
FS1 FS0 CPU PCI 3V66
0 1 100.00 33.33 66.67