Hardware manual

EUROCOM-17-5xx 3 Programmers Reference
Hardware Manual 53
3.3.2 VMEbus
Master
Interface
The master interface of the EUROCOM-17-5xx board supports 8, 16, and
32-bit data transfer cycles in A32, A24, and A16 addressing modes. For a
short overview, see Section1.5 ‘Definition of Board Parameters’.
3.3.2.1 Longword
Access to
Wordwide
Slaves
Two different control lines of the system CIO enable longword breaking
for the A32 and A24/A16 area:
PA3: * 0 : forces A24(A16)/D16 data size on VMEbus
1 : allows A24(A16)/D32 data size on VMEbus
PA4: * 0 : allows A32/D32 data size on VMEbus
1 : forces A32/D16 data size on VMEbus
* specifies the default values set by RMon.
Use the RMon setup menu for changes.
3.3.2.2 Address
Modifier Source
The VIC chip supplies the VMEbus address modifier signals. This is done
by either routing FC0..2 line to AM0..2, or by driving these signals by an
internal address modifier source register of the VIC ($FEC0.10B7). The
AM3..5 lines are driven depending on the actual data size, or by the
address modifier source register. One CIO output signal is used to control
this option:
PA2: * 0 : uses CPU and address size dependent modifiers
1 : uses VIC’s address modifier source register
* specifies the default values set by RMon.
Use the RMon setup menu for changes.
For a detailed description of the address modifier values, see SectionA.2
‘Address Modifiers on VMEbus’.
3.3.2.3 Read-Modify-
Write Cycles
Read-modify-write cycles, like TAS or CAS2 are supported by the
EUROCOM-17-5xx.
The CAS2 instruction has only limited support (see Table1: ‘CAS2
Operations on the Various Busses’). The easiest way to ensure that
CAS2 instructions are indivisible is to have both operands of the
CAS2 instruction within the same memory area (local RAM,
VMEbus, LEB).
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