Hardware manual

EUROCOM-17-5xx 3 Programmers Reference
Hardware Manual 51
Unfortunately the address translation exists only once for the three address
sources (VMEbus, LEB, ILACC). This leads to some restrictions when
the DRAM/VRAM is accessed by A24 addressing from the VMEbus or
the LEB. In this case only parts of the DRAM/VRAM can be reached by
VMEbus A32 addressing or the ILACC.
Example:
1MB slave window size for VMEbus A24 addressing at $C0.0000 to the
first MB of the DRAM:
MBAR = $0000.0000
ASR = $FFF0.0000
SBR = $xxC0.xxxx
SMR = $xx0F.xxxx
In this case VMEbus A32 addressing, the LEB, or the ILACC also reach
only the local address range $0000.0000 to $000F.FFFF, i.e. the first MB
of the DRAM.
To avoid problems, ELTEC recommends that VMEbus A24 slave access is
only used when absolutely necessary and with extreme care. DMA IPINs
should deliver at least A0 to A26 for operation with the default
configuration.
3.2.4 RAM Mirror When the secondary CPU uses copyback or writethrough cache mode for
the DRAM/VRAM and snooping is disabled, the DRAM/VRAM can
become inconsistent with the cache of the secondary CPU. This can cause
problems when such data should be accessed by another device (primary
CPU, VMEbus, ILACC).
To avoid this, the secondary CPU has to use the cache inhibited RAM
mirror ($1000.0000 - $1FFF.FFFF) for global data. The other devices
must also use the mirrored RAM to avoid accessing data cached in the
primary CPU.
3.2.5 RAM Access
from the LEB
Access from the Local Extension Bus (LEB) is done by using a standard
68k-like requester with three-line handshake (/BR, /BG, /BGACK).
During master transfers from the LEB a minimum of 24 address lines
(A0-A23) must be driven. For operation with the default configuration
(256MB slave window) at least A0 to A27 must be driven (see
Section3.2.3 ‘Address Translation’).
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