Hardware manual

3 Programmers Reference EUROCOM-17-5xx
50 Hardware Manual
The ICF1 decoder compares A15 to A8 of the VMEbus with the SBR bits
15 to 8. If a SMR mask bit is set, then the corresponding VMEbus address
bit is ‘don’t care’. For full support of the VIC’s interprocessor
communication features, the EUROCOM-17-5xx has a second A16
decoder called ICF2 decoder. The ESR register allows separate enabling
of the four comparators.
Table29: Enable Slave Register Layout
1 = Decoder enabled
0 = Decoder disabled
Writing the SBR clears all mask bits of the SMR, so that the SBR must be
written before the SMR. Writing the SMR also writes the IFC2 decoder.
3.2.3 Address
Translation
The address presented by the VMEbus, the LEB, or the ILACC is
translated from the '020 bus (A
020
) to the ‘040 bus (A
040
) with the help of
the MBAR (memory base address register) and ASR (address substitution
register) of the IOC-2. The address on the ‘040 bus is calculated using the
following formula:
A
040
= (MBAR & ASR) + (A
020
& /ASR)
& logical AND operation,
+ logical OR operation,
/ logical complement.
The translation is necessary for snooping of the primary CPU to keep its
caches consistent with the memory.
The translated address must always be in the DRAM or VRAM. If
not, the computer crashes in most cases. Accessing mirrored
DRAM/VRAM locations has to be avoided because this causes
inconsistencies between the memory and the caches of the primary
CPU. For all address lines not driven by the source the corresponding
bit position in the ASR must be 1 so that the invalid bits are
substituted.
Reg. Address 7 ... 4 3 2 1 0
ESR $FEC5.C000 unused ICF2
(A16)
ICF1
(A16)
VSTD
(A24)
VEXT
(A32)
i