Hardware manual

EUROCOM-17-5xx 3 Programmers Reference
Hardware Manual 49
3.2 DRAM
3.2.1 RAM Access
from the Local
CPUs
The base address of the DRAM is fixed to $0000.0000.
After reset, the basic EPROM is mapped to address $0000.0000. After
some initialization the firmware enables the DRAM at $0000.0000 via
PA5 of the system CIO.
3.2.2 RAM Access
from the
VMEbus
The base address and window size for VMEbus access is specified by the
slave base address register (SBR), the slave mask register (SMR) and the
enable slave select register (ESR) of the EUROCOM-17-5xx. The SBR
and the SMR are only accessible by the local CPUs by longword write
cycles. They are undefined after reset and must be written before the
EUROCOM-17-5xx can be accessed from the VMEbus. The ESR is
cleared (disabling all slave accesses) by power-on reset and the reset
switch. The ESR can only be accessed by byte write cycles.
Do not use other addresses for the SMR and SBR registers.
The A32 decoder compares A31 to A24 of the VMEbus with the SBR bits
32 to 24 for VMEbus extended access. The A24 decoder compares A23 to
A16 of the VMEbus with the SBR bits 23 to 16 for VMEbus standard
access.
Table28: Slave Base Address Register and Slave Mask Register Layout
Reg. Address 31 24 23 16 15 8 7 0
SMR $FEC0.80F0 A32 Mask A24 Mask ICF1 Mask ICF2
Decoder
SBR $FEC0.80F4 A32
Decoder
ext. access
A24
Decoder
std. access
ICF1
Decoder
short I/O
ICF2
Decoder
short I/O
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