Hardware manual

EUROCOM-17-5xx 1 Specification
Hardware Manual 17
1.3.19 Interrupt
Sources
The EUROCOM-17-5xx allows full utilization of both the powerful
VMEbus interrupt structure and the 68040 CPU design.
1.3.20 Local Extension
Bus
The LEB port of the EUROCOM-17-5xx can carry slave-only, master-
only or master-slave boards. The IRQ line of the LEB is connected to
VIC’s LIRQ5 input. The VIC has to be programmed to generate interrupts
on level 2, because only level 2 IACK cycles are routed to the LEB.
1.3.21 Software The local EUROCOM-17-5xx firmware (RMon) is stored in the on-board
Flash EPROM (FEPROM). RMon provides the basic software layer of the
board. Any operating system or application software is based on the
RMon and uses its functionality:
• Power-On Initialization
• Configuration
• Various Bootstraps
• Externally Callable I/O Functions
• Application Hooks
Power-On Initialization
After RESET or power-on, the local hardware (VIC, serial I/O, CIO,
video, keyboard interface, etc.) must be initialized by the CPU. The
initialization is affected by certain parameters taken either from the on-
board NVRAM or from the Flash EPROM (default values). Hex switch
S902 on the front panel selects whether the NVRAM or the default values
are to be used.
The NVRAM parameters are certified by a checksum. If the checksum test
fails, the default parameters are used independent of the switch setting.
After reset or power-on an automatic selftest routine checks the functional
groups of the board and displays its results.