Hardware manual

1 Specification EUROCOM-17-5xx
16 Hardware Manual
1.3.18 VMEbus
Interface
Each EUROCOM-17-5xx board offers VMEbus master and slave
interfaces. Additionally, VMEbus system controller functions are
available via the VMEbus gate array (VIC).
1.3.18.1 System
Controller
The EUROCOM-17-5xx features a full slot-one system controller,
including SYSCLK, SYSRESET, bus time-out, IACK daisy chain driver,
and a four level arbitration circuit. System controller capabilities are
enabled by switch S3 in position 'SC' on the front panel.
1.3.18.2 VMEbus
Master
Interface
The master interface of the EUROCOM-17-5xx board supports 8, 16, and
32-bit data transfer cycles in A32, A24, and A16 addressing modes.
A special feature is provided to support longword accesses from the local
CPU to D16 VMEbus boards (dynamic bus sizing). Two control lines of
the SCR enable longword breaking for the A32 and A24 area.
The VIC chip supplies the VMEbus address modifier signals. This is done
by either routing FC0..2 line to AM0..2, or by driving these signals by an
internal address modifier source register of the VIC ($FEC0.10B7). The
AM3..5 lines are driven depending on the actual data size, or by the
address modifier source register. One output signal of the system control
register is used to control this option.
The EUROCOM-17-5xx supports master/slave block transfer cycles.
Several options within the VIC chip allow the user to generate different
block transfer cycle types.
The overall transfer rate from one EUROCOM-17-5xx to another
EUROCOM-17-5xx is approximately 35MB/s using D64 block transfer.
1.3.18.3 VMEbus Slave
Interface
The EUROCOM-17-5xx supports A32 and A24 slave access to the
DRAM and an A16 slave interface to access the interprocessor
communication registers. The addresses for all of the slave interfaces are
separately programmable.
For full support of the interprocessor features the EUROCOM-17-5xx has
two A16 slave decoders. One for individual addressing and one for
broadcast addressing of the VIC.