Hardware manual

EUROCOM-17-5xx 1 Specification
Hardware Manual 15
1.3.15 Watchdog
Timer
The watchdog timer monitors the activity of the microprocessor. If the
microprocessor does not access the watchdog timer within the time-out
period of 100ms or 1.6s, a reset pulse is generated. After reset, the
watchdog timer is disabled. The normal time-out period of 100ms/1.6s
becomes effective after the first access to the watchdog timer.
The left decimal point of the hex display located at the front panel is
illuminated to indicate a watchdog reset. This watchdog indicator is only
cleared by power-up reset, the reset switch, a VMEbus SYSRESET, or a
VIC remote reset.
The state of the watchdog indicator can be read by software using bit PA7
of the system control register located in the system CIO.
1.3.16 Status Display The EUROCOM-17-5xx features a seven-segment display on the front
panel and displays hexadecimal values from 0 - F.
This status display ($FEC3.0000) is designed as a read/write register and
uses the least significant nibble of the byte.
The right decimal point of the hex display is controlled by PA0 of the
system control register. The right decimal point is used as an initialization
status by the monitor program. After reset the right decimal point is
illuminated. RMon switches the decimal point off before the user program
in the user EPROM is called.
The LED next to the reset button shows the status of the primary CPU. It
is illuminated when the CPU is running and it is off when the CPU is
halted.
1.3.17 Reset Reset may be initiated by six sources:
• supply voltage drop below 4.75 V or power-up
• reset switch on the front panel
• VMEbus SYSRESET
• VIC remote control reset register
• Watchdog
• CPU RESET instruction