Hardware manual

EUROCOM-17-5xx 1 Specification
Hardware Manual 11
1.3.5 Graphics
Interface
The graphics hardware of the EUROCOM-17-5xx is built in the main by a
video sync generator LM1882, a CLUT BT445 and an address generator
which is implemented in a MACH445. The PLD provides the appropriate
control signals for read/write access, transfer cycles and refresh cycles,
too.
The programmable video timing generator allows the implementation of
different screen resolutions and video standards. The pixel clock stream is
fed to a 256x8x3CLUT and converted by three DACs into a video
signal (with/without composite sync).
The video RAM consists of two VRAMs building a memory array of
1MB size and 32-bit parallel/serial port. The VRAM can be accessed by
different bus masters from the 68040 bus (CPU, VMEbus, SCSI, LEB).
Byte, word, longword and burst accesses are possible speeding up
excessive pixel manipulations. Each byte represents one pixel in 8-bit
resolution mode, so that 256 different colors out of a set of 2
24
can be
displayed at the same time. 1/2/4bits per pixel are also available to speed
up graphics operation.
The overlay RAM is 512K of size and has the same structure as the video
RAM. Overlay operates with 4bits per pixel and is only available when
the video RAM operates in 8bits per pixel. Due to hardware configuration
the overlay RAM is only accessible by word, longword or burst operation.
So, a longword holds the overlay data of four subsequent pixels. The data
of each pixel are held in the lower nibble of each byte in the longword.
The upper nibbles of each byte in the longword are don’t care because
these data lines are not connected to the overlay RAM.
Figure2: Overlay Pixel Data Configuration
XXXX DDDD XXXX DDDD XXXX DDDD XXXX DDDD
Pixel n Pixel n+1 Pixel n+2 Pixel n+3
D31
longword boundary