Hardware manual

EUROCOM-17-5xx 1 Specification
Hardware Manual 9
1.3.2 RAM The DRAM and the video RAM are accessed by the following sources:
• CPU1
• CPU2
• SCSI Controller
• Ethernet Controller
• LEB
• VMEbus
Burst mode is supported for accesses of:
• CPU1
• CPU2
• SCSI Controller
• VMEbus BLT
The base address of the DRAM seen from the CPUs is fixed to
$0000.0000. To avoid programming of the MMU, the DRAM and VRAM
are mirrored as non-cacheable RAM.
The base address for accessing the RAM from the VMEbus as well as the
window size is programmable. The on-board firmware uses hex switch
S901 to program the VMEbus address decoder and mask registers.
When using A24 addressing, including accesses from the LEB, to access
the EUROCOM-17-5xx RAM, the address translation logic must be
programmed to supply the local addresses A(24) to A(26). In this case
either the video RAM or the DRAM can be reached from VMEbus
(including A32 addressing) but not both (see Section3.2.3 ‘Address
Translation’).
The following table summarizes the usable bandwidth of the RAM
including precharge and refresh.
Table2: Usable Bandwidth of the RAM
Bus Clock 40MHz: (MB/s) 33MHz: (MB/s) 25MHz: (MB/s)
DRAM read 70 58 50
DRAM write 79 66 50
VRAM read 53 44 40
VRAM write 53 44 40
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