Hardware manual

1 Specification EUROCOM-17-5xx
8 Hardware Manual
CPU1 handles all interrupts generated by the VIC. CPU2 can interrupt
CPU1 via the interprocessor communication module switch facility of the
VIC. The secondary CPU2 is interrupted by accessing a separate mailbox
location by CPU1, by the LEB or by the VIC timer (refer to Table50:
‘CPU2CON As Seen by Primary CPU’). Additionally, VMEbus interrupts
can be handled with some restrictions by the secondary CPU. IACK
cycles of CPU1 are always routed to the VIC while those of CPU2 always
use autovector interrupt acknowledge mode.
Non-interruptable read-modify-write cycles (TAS command) are
supported between VMEbus, CPU1, and CPU2. RMC cycles from the
VMEbus to the local RAM are only indivisible when they are byte size.
CAS2 instructions have limited support.
The secondary CPU may not be used by the application. All system
functions are served by the primary CPU.
Both CPUs can execute the same code, in case it is reentrant of course.
Each CPU can find out whether it is the primary or secondary CPU by
reading bit6 of the secondary CPU control register (CPU2CON).
Table1: CAS2 Operations on the Various Busses
1st op 2nd op indivisible
local RAM local RAM yes
'020 bus (LEB) local RAM yes
VMEbus local RAM yes
local RAM '020 bus (LEB) no
'020 bus (LEB) '020 bus (LEB) yes
VMEbus '020 bus (LEB) yes
local RAM VMEbus no
'020 bus (LEB) VMEbus no
VMEbus VMEbus yes