Hardware manual

EUROCOM-17-5xx 1 Specification
Hardware Manual 7
1.3 Technical Details
The EUROCOM-17-5xx consists of the following main blocks:
• CPUs
• RAM Module
• Basic EPROM
• User EPROM
• Graphics Interface
• Keyboard Interface
• Ethernet Interface
• SCSI Interface
• Serial I/0
• Parallel I/O
• CIO Counters/Timers
• Parameter RAM and Real-Time Clock
• Revision EEPROM
• VIC Timer
• Watchdog Timer
• Status Display
• Reset
• VMEbus Interface
• Interrupt Sources
• Local Extension Bus
• Software
• Connectors
1.3.1 CPUs Equipped with Motorola’s 68040 CPU, the CPUs are clocked with 25, 33
or 40MHz. All internal bus operations are synchronous to this clock. The
CPUs use burst mode only to access main memory and video RAM.
Although both CPUs are connected mainly in parallel, a distinction into a
primary and a secondary CPU can be made: The primary CPU (CPU1)
receives all system interrupts and is always started first. The secondary
CPU (CPU2) can be released from the reset state afterwards by the
primary CPU (refer to Table50: ‘CPU2CON As Seen by Primary CPU’).