Hardware manual

1 Specification EUROCOM-17-5xx
4 Hardware Manual
The EUROCOM-17-5xx is a highly integrated high-performance single-
board VMEbus computer with graphics display. It is designed to offer as
many features as possible on a single slot VMEbus board. Suitable
intelligent or high integrated components are used to achieve this density
of computing power.
There are two on-board 68040 CPUs, each clocked at 25, 33 or 40MHz.
On-chip caches for program and data (4KB capacity each) and the on-
chip floating-point units allow 35MIPS/ 5.6MFLOPS for each CPU.
Additionally, backward compatibility with existing 68000-family
software is guaranteed. Due to the on-chip caches, neither of the CPUs
makes full use of the available bus bandwidth. Thus, parallelizing two
CPUs (closely coupled) puts only a small burden (15%) on processing
speed for most programs.
The main memory is placed on a separate memory module. This easily
allows to expand the memory up to 252MB without making any changes
necessary at the CPU board. The available memory modules supply
different memory resources such as up to 64MB DRAM, 4MB Flash
EPROM and up to 2MB battery backed SRAM. The main memory can
directly be accessed via the 32-bit processor bus.
The main memory is organized in two banks of interleaved DRAM.
Therefore, burst mode transfers allow 70MB/s on reads. Due to a buffered
write mechanism, the transfer rate for writes is even bigger (79MB/s).
This is useful during cache flushes where the CPU may write large
amounts of data.
The major drawback of the 68040 is the deletion of dynamic bus sizing.
This requires 68020/30 applications to be modified if they access word
devices with longword instructions. The longword accesses have to be
split by software into two word accesses which slows down the
performance. Instead of this, the IOC-2 hardware generates the needed
bus cycles if the addressed device acknowledges a smaller data size than
the CPU requested.