Hardware manual

EUROCOM-17-5xx 3 Programmers Reference
Hardware Manual 91
3.21 Indivisible Cycle Operation
3.21.1 Deadlock
Resolution
When a CPU performs a locked cycle to the '020 bus (e.g. TAS to the
VMEbus) and someone wants to access the '040 bus from the '020 bus
(e.g. slave access from VMEbus to the local RAM) there is a deadlock
situation. On normal reads or writes such a deadlock is resolved by
sending a retry acknowledge to the CPU. On locked cycles this does not
work because the arbiter does not grant the bus from the current bus
master as long as /LOCK is active. Such deadlocks are resolved by sending
an error acknowledge to the CPU. Then there must be a bus error trap
handler that inspects the stack frame whether there was a locked cycle or
not. If not, normal bus error handling is continued. Else the locked cycle is
retried by simply performing a RTE instruction. The trap handler also
should inspect the VIC's bus error status register bits 5 and 6 whether there
was a bus error. If so also normal bus error handling should be done to
prevent that the trap handler retries the locked cycle infinitely.
3.21.2 TAS Violation If a semaphore resides in a region that can be cached in the '040 in
copyback mode TAS violation can occur if:
• the semaphore resides in a dirty cache line in the cache of the '040, and
the semaphore is set,
• an alternate master performs the read of a TAS,
• the '040 snoops the read and supplies that the semaphore is set,
• the '040 clears the semaphore (in the cache),
• the alternate master performs the write of the TAS,
• the '040 snoops the write so that the semaphore is set again.
As a result of this the clearing of the semaphore is lost! This can be
avoided by using the CAS instruction to clear the semaphore.