Hardware manual

3 Programmers Reference EUROCOM-17-5xx
88 Hardware Manual
3.19.4 Cache
Coherency and
Snooping
To maintain cache coherency in a multi master system, the ‘040 has the
capability of snooping. Snooping can be enabled via snoop control register
at $FEC5.E000 (write only).
EUROCOM-17-5xx snooping:
Table52: Snoop Control Register Layout for EUROCOM-17-5xx
Table53: Snoop Control Encoding for EUROCOM-17-5xx
After reset snooping of both CPUs is disabled. Normally, the primary
CPU should use SC1=0 and SC0=1 snoop mode. This ensures cache
coherency with all non caching alternate bus masters. When data should
be cached in both CPUs, the secondary CPU must also use this snooping
mode and both CPUs must use writethrough caching mode for that data.
The EUROCOM-17-5xx does not support copyback cache mode in both
CPUs for the same memory location. Data that is copyback in one CPU
must be cache inhibited in the other.
Snooping of the secondary CPU can only be enabled when the secondary
CPU is running otherwise the EUROCOM-17-5xx will crash (i.e. the
SRESET bit in the CPU2CON register always has to be set before one of
the snoop control bits in the snoop control register is set for the secondary
CPU).
Register Address 7 - 4 3 2 1 0
SNCR $FEC5.E000 unused
SC1 for
secondary
CPU
SC0 for
secondary
CPU
SC1 for
prima-
ry CPU
SC0 for
prima-
ry CPU
Requested Snoop Operation
SC1 SC0 Alternate Bus Master Read
Access
Alternate Bus Master Write
Access
0 0 Inhibit Snooping Inhibit Snooping
0 1 Supply Dirty Data and Leave Dirty Sink Byte/Word/Longword
1 0 Supply Dirty Data and Mark Line
Invalid
Invalidate Line
1 1 Reserved (Snoop Inhibited) Reserved (Snoop Inhibited)
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