Hardware manual

EUROCOM-17-5xx 3 Programmers Reference
Hardware Manual 87
3.19.3 VMEbus
Interrupts for
the Secondary
CPU
The EUROCOM-17-5xx allows to route VMEbus interrupts to the
secondary CPU. Therefore, some restrictions must be considered.
• Only one VMEbus interrupt of IRQ1, IRQ3, IRQ5, IRQ7 can be routed
to the secondary CPU. The adequate level is selected via J1703. For the
secondary CPU, an autovectored level2 interrupt will be generated if a
VMEbus interrupt occurs.
• If an VMEbus IRQ is routed to the secondary CPU, it is necessary to
disable this VMEbus IRQ in the VIC for the primary CPU.
• The interrupter must be able to support RORA for the secondary CPU
performs always autovector interrupts.
• The secondary CPU never starts an IACK cycle on the VMEbus on
respond to a VMEbus interrupt request. There will be only autovectored
interrupts for the secondary CPU.
Table51: CPU2CON As Seen by Secondary CPU
Bit
Pos.
Name Read/
Write
Description
7 MIPEND read Mailbox Interrupt Pending
0 = interrupt acknowledged by secondary CPU
1 = mailbox interrupt pending
6 CPUID read CPU Identification
always 0 when read by secondary CPU
5 VICIRQ read VIC Interrupt Request
0 = no interrupt from VIC clock
1 = interrupt from VIC clock
2
1
0
SICF2
SICF1
SICF0
write
write
write
Secondary CPU Interrupt Control Function 0-2.
SICF2 SICF1 SICF0 Function
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
disable IRQ from VIC clock
enable IRQ from VIC clock
disable IRQ from LEB
enable IRQ from LEB
IACK for IRQ from VIC
IACK for mailbox IRQ
disable VMEbus IRQs for CPU2
enable VMEbus IRQs for CPU2