Hardware manual

3 Programmers Reference EUROCOM-17-5xx
86 Hardware Manual
3.19.2 Interrupting
the Primary
CPU
The primary CPU is interrupted by the secondary CPU by writing bits0-3
of the VIC’s interprocessor communication switch register ($FEC0.105F).
A clear to set transition of a bit interrupts the primary CPU when the
corresponding bit in the ICMS interrupt control register ($FEC0.1047) is
clear (see also VIC data sheet).
Table50: CPU2CON As Seen by Primary CPU
Bit
Pos.
Name Read/
Write
Description
7 MIPEND read Mailbox Interrupt Pending
0 = interrupt acknowledged by secondary CPU
1 = mailbox interrupt pending
6 CPUID read CPU Identification
always 1 when read by primary CPU
5 SRESET write Secondary CPU Reset
This bit is connected to the reset input of the secondary
CPU.
0 = reset secondary CPU
1 = run secondary CPU
2
1
0
SIPL2
SIPL1
SIPL0
write
write
write
Secondary CPU Interrupt Priority Lines 0-2.
These bits are connected to the interrupt inputs of the
secondary CPU. If one or more of these bits are set, an
interrupt is generated for the secondary CPU and bit 7
(MIPEND) of this register is set.
SIPL2 SIPL1 SIPL0 Interrupt Level Generated
0 0 0
0 0 1
0 1 0
. . .
1 1 0
no interrupt
1
2
.
7
After the interrupt acknowledge of the secondary CPU,
SIPL0-2 and MIPEND are cleared.