Hardware manual

EUROCOM-17-5xx 3 Programmers Reference
Hardware Manual 85
3.19 Secondary CPU Support
The revision register must contain a dual-CPU order number to
enable secondary CPU support. On single-CPU boards, the second
CPU can be installed, but may not be usable. So, installing a second
CPU must be done only at the factory!
The secondary CPU is controlled via the CPU2CON at $FEC5.8000. To
run the secondary CPU the primary CPU must prepare stack pointer and
program counter and release the secondary CPU from reset by setting the
appropriate bits of the CPU2CON.
move.b #$00, $FEC58000 ; reset secondary CPU
move.l #STACK, $0 ; prepare stack pointer
move.l #PCOUNT, $4 ; prepare program counter
move.b #$20, $FEC58000 ; run secondary CPU
3.19.1 Interrupting
the Secondary
CPU
The secondary CPU can be interrupted by the primary CPU, by the VIC
timer (positive edge-sensitive), the LEB (negative level-sensitive), and
VMEbus. If the primary CPU writes bit0-2 of the CPU2CON, an interrupt
is generated for the secondary CPU. When servicing this interrupt, the
secondary CPU has to write $05 to the CPU2CON to clear the interrupt
and the mailbox interrupt pending flag. Interrupts from the VIC timer, the
LEB, or the VMEbus are enabled or disabled by the secondary CPU by
writing the appropriate code to the CPU2CON (see Table50: ‘CPU2CON
As Seen by Primary CPU’).
After reset the interrupts from the VIC timer and LEB are disabled. The
interrupt routine for the VIC timer has to write $04 to the CPU2CON to
clear the pending interrupt and the VIC interrupt request flag. All
interrupts use autovector interrupt acknowledge cycles. The interrupt
priority encoder for the secondary CPU uses level4 for the VIC timer and
level3 for the LEB interrupts.
!