Hardware manual

3 Programmers Reference EUROCOM-17-5xx
80 Hardware Manual
3.17 System Control Register (SCR)
The EUROCOM-17-5xx features several status and control bits to
monitor and change the system control signals. These are implemented
using port lines of the system CIO. Reset initializes all ports as input. The
default values are set during the RMon initialization routine.
All outputs of the CIO are pulled high to ensure a valid logic level after
reset.
Table47: System Control Register Layout (System CIO)
Bit No. Type Name Description
PA7 Input WDS Watchdog Status
0 = Watchdog Reset
1 = Normal Reset
PA6 Output BLK Blank Display
0 = Display enabled
1 = Display disabled
PA5 Output RESCYC Reset Cycle
0 = Address Decoder normal operation (default)
1 = Address Decoder reset operation (reset
condition)
PA4 Output DSCTRL0 VMEbus A32 Data Size Control
0 = normal longword operation for A32 (default)
1 = breaks longword cycles into two word cycles
PA3 Output DSCTRL1 VMEbus A24 Data Size Control
0 = normal longword operation for A24
1 = breaks longword cycles into two word cycles
(default)
PA2 Output ASCTRL VMEbus Address Modifier Source Control
0 = normal operation FC0..2 -> AM3..5
1 = VMEbus Address Modifier
from VICs Address Modifier Source Register
PA1 Output CACTRL VMEbus Cache Control
0 = disables caching of VMEbus data (default)
1 = enables caching of VMEbus data
PA0 Output INIT Initialization Indicator on Front Panel
0 = on
1 = off
PB7..0 Input HEXSW Read Hex Switch on Front Panel
PC3..0 Output DISPLAY Write Hex Display on Front Panel
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