Hardware manual

3 Programmers Reference EUROCOM-17-5xx

72 Hardware Manual

3.10 IOC-2

ELTEC’s Input/Output Controller (IOC-2) is an ASIC intended to

maximize the performance of ELTEC’s CPU boards. The IOC-2 is

specially designed as data/address bridge between a 68040-type local bus

and VIC068/064 to support fast VMEbus master/slave block transfers. A

second main function is a universal programmable I/O bus interface with

an appropriate address decoder.

3.10.1 Register Set All 25 IOC-2 registers are read/write accessible using longword transfer

cycles only. The internal address decoder reserves an IOC-2 address space

of 64KB. The following register map shows all internal registers and their

corresponding register offset address. The complete CPU register address

is calculated by:

IOALR value

+ Register OFFSET address

1. Default register value: $FEC0.0000

Table43: Register Map

Offset Addr. Symbol Name Reset Value

I/O Bus Interface Registers:

$70000 IOALR I/O Address Location Register $FEC0.0000

$70004 IODCR0 I/O Device Control Register 0 $0000.0000

$70008 IODCR1 I/O Device Control Register 1 $0000.0000

$7000C IODCR2 I/O Device Control Register 2 $0000.0000

$70010 IODCR3 I/O Device Control Register 3 $0000.0000

$70014 IODCR4 I/O Device Control Register 4 $0000.0000

$70018 IODCR5 I/O Device Control Register 5 $0000.0000

$7001C IODCR6 I/O Device Control Register 6 $0000.0000

$70020 IODCR7 I/O Device Control Register 7 $0000.0000

$70024 IODCR8 I/O Device Control Register 8 $0000.0000

$70028 IODCR9 I/O Device Control Register 9 $0000.0000